static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
{
int64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
Val = AArch64_AM_decodeLogicalImmediate(Val, 64);
switch(MI->flat_insn->id) {
default:
printInt64Bang(O, Val);
break;
case ARM64_INS_ORR:
case ARM64_INS_AND:
case ARM64_INS_EOR:
case ARM64_INS_TST:
// do not print number in negative form
if (Val >= 0 && Val <= HEX_THRESHOLD)
SStream_concat(O, "#%u", (int)Val);
else
SStream_concat(O, "#0x%"PRIx64, Val);
break;
}
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)Val;
MI->flat_insn->detail->arm64.op_count++;
}
}
static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
{
int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum));
printInt64Bang(O, val);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int)val;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
MI->flat_insn->detail->arm64.op_count++;
}
}
}
static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int64_t val = Scale * MCOperand_getImm(MO);
printInt64Bang(O, val);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
MI->flat_insn->detail->arm64.op_count++;
}
}
}
}
