/** * Print the values of all of the LPC47M10X2's configuration registers. * * NOTE: The LPC47M10X2 must be in config mode when this function is called. * * @param dev Pointer to structure describing a Super I/O device. */ static void dump_pnp_device(device_t dev) { int i; print_debug("\n"); for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) { u8 register_value; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } /* * Skip over 'register' that would cause exit from * configuration mode. */ if (i == 0xaa) register_value = 0xaa; else register_value = pnp_read_config(dev, i); print_debug_char(' '); print_debug_hex8(register_value); if ((i & 0x0f) == 0x0f) print_debug("\n"); } print_debug("\n"); }
static void dump_spd_data(void) { int dimm, offset, regs; unsigned int val; for (dimm = 0; dimm < 8; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); print_debug("\n"); val = get_spd_data(dimm, 0); if (val == 0xff) { regs = 256; } else if (val == 0x80) { regs = 128; } else { print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { print_debug(" Offset "); print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(dimm, offset)); print_debug("\n"); } } }
static void dump_spd_data(const struct mem_controller *ctrl) { int dimm, offset, regs; unsigned int val; for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) { print_debug("SPD Data for DIMM "); print_debug_hex8(dimm); print_debug("\n"); val = get_spd_data(ctrl, dimm, 0); if (val == 0xff) { regs = 256; } else if (val == 0x80) { regs = 128; } else { print_debug("No DIMM present\n"); regs = 0; } for (offset = 0; offset < regs; offset++) { print_debug(" Offset "); print_debug_hex8(offset); print_debug(" = 0x"); print_debug_hex8(get_spd_data(ctrl, dimm, offset)); print_debug("\n"); } } }
unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address) { unsigned char error = 0; if ((smbus_check_stop_condition(smbus_io_base))) { error = 1; goto err; } if ((smbus_start_condition(smbus_io_base))) { error = 2; goto err; } if ((smbus_send_slave_address(smbus_io_base, device << 1))) { error = 3; goto err; } smbus_ack(smbus_io_base, 1); if ((smbus_send_command(smbus_io_base, address))) { error = 4; goto err; } if ((smbus_start_condition(smbus_io_base))) { error = 5; goto err; } if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) { error = 6; goto err; } if ((smbus_stop_condition(smbus_io_base))) { error = 7; goto err; } return smbus_get_result(smbus_io_base); err: print_debug("SMBUS READ ERROR:"); print_debug_hex8(error); print_debug(" device:"); print_debug_hex8(device); print_debug("\n"); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); outb(0x0, smbus_io_base + SMB_STS); return 0xFF; }
void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; id = get_node_core_id_x(); //FIXME: for USBDEBUG you need to make sure dbg_info get assigned in AP print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); /* go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp */ __asm__ volatile ( "movl %0, %%edi\n\t" "jmp *%%edi\n\t" :: "a"(ret_addr) ); }
void hardwaremain(int ret_addr) { struct sys_info *sysinfo = &sysinfo_car; // in CACHE struct sys_info *sysinfox = ((CONFIG_RAMTOP) - sizeof(*sysinfox)); // in RAM struct node_core_id id; id = get_node_core_id_x(); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n"); train_ram(id.nodeid, sysinfo, sysinfox); /* go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp */ __asm__ volatile ( "movl %0, %%edi\n\t" "jmp *%%edi\n\t" :: "a"(ret_addr) ); }
static void enable_smbus(void) { device_t dev; unsigned char c; /* Power management controller */ dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); } // set IO base address to SMBUS_IO_BASE pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); // Enable SMBus c = pci_read_config8(dev, 0xd2); c |= 5; pci_write_config8(dev, 0xd2, c); /* make it work for I/O ... */ dev = pci_locate_device(PCI_ID(0x1106, 0x8231), 0); c = pci_read_config8(dev, 4); c |= 1; pci_write_config8(dev, 4, c); print_debug_hex8(c); print_debug(" is the comm register\n"); print_debug("SMBus controller enabled\n"); }
int spd_read_byte(unsigned int device, unsigned int address) { print_debug("spd_read_byte dev "); print_debug_hex8(device); if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } print_debug(" addr "); print_debug_hex8(address); print_debug(" returns "); print_debug_hex8(spdbytes[address]); print_debug("\n"); return spdbytes[address]; }
static u8 spd_read_byte(u8 device, u8 address) { print_debug("spd_read_byte dev "); print_debug_hex8(device); if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } print_debug(" addr "); print_debug_hex8(address); print_debug(" returns "); print_debug_hex8(spdbytes[address]); print_debug("\n"); return spdbytes[address]; }
static inline void change_i2c_mux(unsigned device) { #define SMBUS_HUB 0x18 int ret; print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x01, device); print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); }
static inline void print_debug_sdram_8(const char *strval, uint32_t val) { #if CONFIG_CACHE_AS_RAM printk(BIOS_DEBUG, "%s%02x\n", strval, val); #else print_debug(strval); print_debug_hex8(val); print_debug("\n"); #endif }
void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); print_debug("\n"); for (i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); print_debug_char(' '); print_debug_hex8(val); if ((i & 0x0f) == 0x0f) { print_debug("\n"); } } }
static void power_down_reset_check(void) { uint8_t cmos; cmos=cmos_read(RTC_BOOT_BYTE)>>4 ; print_debug("Boot byte = "); print_debug_hex8(cmos); print_debug("\n"); if((cmos>2)&&(cmos&1)) full_reset(); }
void smbus_reset(void) { outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); smbus_wait_until_ready(); print_debug("After reset status "); print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT)); print_debug("\n"); }
static void usb2_init(struct device *dev) { u32 base; struct resource *res; print_debug("USB 2.0 INIT:---------->\n"); //-------------- enable USB2.0 (SiS7002) ------------------------- { u8 temp8; int i=0; while(SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); temp8 &= SiS_SiS7002_init[i][1]; temp8 |= SiS_SiS7002_init[i][2]; pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); i++; }; } res = find_resource(dev, 0x10); if(!res) return; base = res->base; printk(BIOS_DEBUG, "base = 0x%08x\n", base); write32(base+0x20, 0x2); //----------------------------------------------------------- #if DEBUG_USB2 { int i; print_debug("****** USB 2.0 PCI config ******"); print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } print_debug("\n"); } #endif print_debug("USB 2.0 INIT:<----------\n"); }
static void dump_spd_registers(void) { #if CONFIG_DEBUG_RAM_SETUP int i; print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; device = DIMM_SPD_BASE + i; if (device) { int j; print_debug("dimm: "); print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { int status; unsigned char byte; if ((j & 0xf) == 0) { print_debug("\n"); print_debug_hex8(j); print_debug(": "); } status = smbus_read_byte(device, j); if (status < 0) { print_debug("bad device\n"); break; } byte = status & 0xff; print_debug_hex8(byte); print_debug_char(' '); } print_debug("\n"); } } #endif }
static inline void change_i2c_mux(unsigned device) { #define SMBUS_SWITCH1 0x48 #define SMBUS_SWITHC2 0x49 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); smbus_send_byte_one(SMBUS_SWITCH2, (device >> 4) & 0x0f); int ret; print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte(SMBUS_SWITCH1, device); print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); ret = smbus_send_byte_one(SMBUS_SWITCH2, device); print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); }
static int smbus_wait_until_ready(void) { unsigned char c; unsigned long loops; loops = SMBUS_TIMEOUT; do { smbus_delay(); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); while((c & 1) == 1) { print_debug("c is "); print_debug_hex8(c); print_debug("\n"); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); /* nop */ } } while(--loops); return loops?0:-1; }
static void goto_test(void) { int i; print_debug("goto_test\n"); i = 0; goto bottom; { top: print_debug("i = "); print_debug_hex8(i); print_debug("\n"); i = i + 1; } bottom: if (i < 10) { goto top; } }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 // third node RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, // four node RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { { /* Read FIDVID_STATUS */ msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } } else { print_debug("Changing FIDVID not supported\n"); } #endif #if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } #endif allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 int i; for(i=0;i<4;i++) { activate_spd_rom(&cpu[i]); dump_smbus_registers(); } #endif memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 print_pci_devices(); #endif #if 0 // dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
static void print_val(char *str, int val) { print_debug(str); print_debug_hex8(val); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); /* Setup the mcp55 */ mcp55_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); uart_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); #if CONFIG_USBDEBUG mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); early_usbdebug_init(); #endif console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if SET_FIDVID == 1 { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif init_timer(); // Need to use TMICT to synconize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* all ap stopped? */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* FIXME: This should be part of the Super I/O code/config. */ pnp_enter_ext_func_mode(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); console_init(); report_bist_failure(bist); /* Halt upon BIST failure. */ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); #endif setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is * started, esp for two way system (there may be APIC ID conflicts in * that case). */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ #if CONFIG_SET_FIDVID { msr_t msr = rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); { msr_t msr = rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); } #endif init_timer(); /* Need to use TMICT to synconize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); /* fidvid change will issue one LDTSTOP and the HT change will be effective too. */ if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl in sysinfo now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* All AP stopped? */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); /* bsp switch stack to RAM and copy sysinfo RAM now. */ post_cache_as_ram(); }
static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 Channel; u32 TestAddr0; u8 _DisableDramECC = 0, _Wrap32Dis = 0, _SSE2 = 0; u16 MaxRdLatDly; u8 RcvrEnDly = 0; u32 PatternBuffer[60]; // FIXME: why not 48 + 4 u32 Margin; u32 addr; u32 cr4; u32 lo, hi; u8 valid; u32 pattern_buf; cr4 = read_cr4(); if(cr4 & (1<<9)) { /* save the old value */ _SSE2 = 1; } cr4 |= (1<<9); /* OSFXSR enable SSE2 */ write_cr4(cr4); addr = HWCR; _RDMSR(addr, &lo, &hi); if(lo & (1<<17)) { /* save the old value */ _Wrap32Dis = 1; } lo |= (1<<17); /* HWCR.wrap32dis */ lo &= ~(1<<15); /* SSEDIS */ /* Setting wrap32dis allows 64-bit memory references in real mode */ _WRMSR(addr, lo, hi); _DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat); pattern_buf = SetupMaxRdPattern(pMCTstat, pDCTstat, PatternBuffer); for (Channel = 0; Channel < 2; Channel++) { print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1); pDCTstat->Channel = Channel; if( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel) break; /*if ganged mode, skip DCT 1 */ TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid); if(!valid) /* Address not supported on current CS */ continue; /* rank 1 of DIMM, testpattern 0 */ WriteMaxRdLat1CLTestPattern_D(pattern_buf, TestAddr0); MaxRdLatDly = mct_GetStartMaxRdLat_D(pMCTstat, pDCTstat, Channel, RcvrEnDly, &Margin); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly start ", MaxRdLatDly, 2); print_debug_dqs("\tMaxRdLatencyTrain52: MaxRdLatDly Margin ", Margin, 2); while(MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */ mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly); ReadMaxRdLat1CLTestPattern_D(TestAddr0); if( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS) break; SetTargetWTIO_D(TestAddr0); FlushMaxRdLatTestPattern_D(TestAddr0); ResetTargetWTIO_D(); MaxRdLatDly++; } print_debug_dqs("\tMaxRdLatencyTrain53: MaxRdLatDly end ", MaxRdLatDly, 2); mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly + Margin); } if(_DisableDramECC) { mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC); } if(!_Wrap32Dis) { addr = HWCR; _RDMSR(addr, &lo, &hi); lo &= ~(1<<17); /* restore HWCR.wrap32dis */ _WRMSR(addr, lo, hi); } if(!_SSE2){ cr4 = read_cr4(); cr4 &= ~(1<<9); /* restore cr4.OSFXSR */ write_cr4(cr4); } #if DQS_TRAIN_DEBUG > 0 { u8 Channel; print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n"); for(Channel = 0; Channel<2; Channel++) { print_debug("Channel:"); print_debug_hex8(Channel); print_debug(": "); print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] ); print_debug("\n"); } } #endif }
static void aza_init(struct device *dev) { u32 base; struct resource *res; u32 codec_mask; print_debug("AZALIA_INIT:---------->\n"); //-------------- enable AZA (SiS7502) ------------------------- { u8 temp8; int i=0; while(SiS_SiS7502_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); temp8 &= SiS_SiS7502_init[i][1]; temp8 |= SiS_SiS7502_init[i][2]; pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); i++; }; } //----------------------------------------------------------- // put audio to D0 state pci_write_config8(dev, 0x54,0x00); #if DEBUG_AZA { int i; print_debug("****** Azalia PCI config ******"); print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } print_debug("\n"); } #endif res = find_resource(dev, 0x10); if(!res) return; base = res->base; printk(BIOS_DEBUG, "base = 0x%08x\n", base); codec_mask = codec_detect(base); if(codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } print_debug("AZALIA_INIT:<----------\n"); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); console_init(); enable_rom_decode(); printk(BIOS_INFO, "now booting... \n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); printk(BIOS_INFO, "now booting... All core 0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); print_debug_hex8(needs_reset); needs_reset |= optimize_link_incoherent_ht(sysinfo); print_debug_hex8(needs_reset); needs_reset |= k8t890_early_setup_ht(); print_debug_hex8(needs_reset); vt8237_early_network_init(NULL); vt8237_early_spi_init(); if (needs_reset) { printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); printk(BIOS_DEBUG, "FAILED!\n"); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ /* allow LDT STOP asserts */ vt8237_sb_enable_fid_vid(); enable_fid_change(); print_debug("after enable_fid_change\n"); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_default_resource_map(); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 dump_smbus_registers(); #endif memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); #if 0 uint8_t tmp = 0; pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); /* Is serial flash enabled? Then enable writing to serial flash. */ if (tmp & 0x0e) { pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); pnp_set_logical_device(GPIO_DEV); /* Set Serial Flash interface to 0x0820 */ pnp_write_config(GPIO_DEV, 0x64, 0x08); pnp_write_config(GPIO_DEV, 0x65, 0x20); } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); #endif ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif init_timer(); // Need to use TMICT to synconize FID/VID needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* all ap stopped? */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); //enable RTC pc87417_enable_dev(RTC_DEV); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_ms9185_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); //bx_a010- wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif #if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } #endif allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 int i; for(i=0;i<2;i++) { activate_spd_rom(sysinfo->ctrl+i); dump_smbus_registers(); } #endif #if 0 int i; for(i=1;i<256;i<<=1) { change_i2c_mux(i); dump_smbus_registers(); } #endif //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 print_pci_devices(); #endif #if 0 // dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif post_cache_as_ram(); }
static void ide_init(struct device *dev) { struct southbridge_sis_sis966_config *conf; /* Enable ide devices so the linux ide driver will work */ uint32_t dword; uint16_t word; uint8_t byte; conf = dev->chip_info; print_debug("IDE_INIT:---------->\n"); //-------------- enable IDE (SiS5513) ------------------------- { uint8_t temp8; int i=0; while(SiS_SiS5513_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]); temp8 &= SiS_SiS5513_init[i][1]; temp8 |= SiS_SiS5513_init[i][2]; pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8); i++; }; } //----------------------------------------------------------- word = pci_read_config16(dev, 0x50); /* Ensure prefetch is disabled */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); printk(BIOS_DEBUG, "IDE0\n"); } word |= (1<<12); word |= (1<<14); pci_write_config16(dev, 0x50, word); byte = 0x20 ; // Latency: 64-->32 pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); dword |= 12; pci_write_config32(dev, 0xf8, dword); #if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif #if DEBUG_IDE { int i; print_debug("****** IDE PCI config ******"); print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ print_debug("\n"); print_debug_hex8(i); print_debug(": "); } print_debug_hex32(pci_read_config32(dev,i)); print_debug(" "); } print_debug("\n"); } #endif print_debug("IDE_INIT:<----------\n"); }