void write_ngrams_to_file(std::unordered_map<int,size_t>*map, FILE *fp,size_t n)
{
size_t total = 0;
int i = 0;
std::vector<std::pair<size_t, int> > v =
std::vector<std::pair<size_t, int> >(map->size());
for(auto it = map->begin(); it!=map->end(); ++it) {
total += it->second;
v[i++] = std::pair<size_t, int>(it->second,it->first);
}
struct {
bool operator() (const std::pair<size_t, int>& lhs,
const std::pair<size_t, int>& rhs) const{
if(lhs.first == rhs.first) return lhs.second < rhs.second;
return lhs.first > rhs.first;
}
} comp;
std::sort(v.begin(), v.end(), comp);
for(auto it = v.begin(); it != v.end(); ++it) {
size_t amt = it->first;
fprintf(fp, "%d:\t", i);
print_val(it->second, n, fp);
fprintf(fp,"\t\t%lu\t\t%f%%\n",amt,(((float)amt)/((float)total))*100.0);
}
}
int main(int argc, char *argv[])
{
int loop;
for (loop = 0; loop < 10; loop++)
print_val(loop);
exit(EXIT_SUCCESS);
}
void print_const_decl(constdecllist_t const_decls, int indent)
{
for (unsigned i = 0; i < const_decls.size; ++i)
{
print_indent(indent);
printf("const %s %s = ", algo_to_c_type(const_decls.data[i]->type),
const_decls.data[i]->ident);
print_val(const_decls.data[i]->val);
printf(";\n");
}
}
static void print_attrvals(NODE *n)
{
NODE *attr;
for(; n != NULL; n = n->u.LIST.next) {
attr = n->u.LIST.self;
printf("%s =", attr->u.ATTRVAL.attrname);
print_val(attr->u.ATTRVAL.value);
if (n->u.LIST.next != NULL)
printf(", ");
}
}
void print_expression(struct expr *e)
{
switch (e->exprtype)
{
case valtype:
print_val(e->val.val);
break;
case binopexprtype:
printf("(");
print_expression(e->val.binopexpr.e1);
printf(" %s ", getopstr(e->val.binopexpr.op));
print_expression(e->val.binopexpr.e2);
printf(")");
break;
case unopexprtype:
printf("(");
printf("%s ", getopstr(e->val.unopexpr.op));
print_expression(e->val.unopexpr.e);
printf(")");
break;
case arrayexprtype:
print_expression(e->val.arrayexpr.e1);
for (unsigned i = 0; i < e->val.arrayexpr.indices.size; ++i)
{
printf("[");
print_expression(list_nth(e->val.arrayexpr.indices, i));
printf(" - 1]");
}
break;
case identtype:
if (e->argref)
printf("*(%s)", e->val.ident);
else
printf("%s", e->val.ident);
break;
case dereftype:
printf("*");
print_expression(e->val.deref.e);
break;
case funcalltype:
printf("%s(", e->val.funcall.fun_ident);
print_arglist(e->val.funcall.args);
printf(")");
break;
case structelttype:
printf("(");
print_expression(e->val.structelt.record);
printf(").%s", e->val.structelt.field);
break;
default:
printf("expr not handled yet in print_expression\n");
}
}
void Trick::RtiEventBase::print_rti () {
message_publish (MSG_NORMAL, "----------------------------------------\n");
message_publish (MSG_NORMAL, " reference: %s\n", ref->reference);
message_publish (MSG_NORMAL, " num_index: %d\n", ref->num_index);
message_publish (MSG_NORMAL, " units: %s\n", ref->units);
message_publish (MSG_NORMAL, " pointer_present: %d\n", ref->pointer_present);
message_publish (MSG_NORMAL, " address: %x\n", ref->address);
message_publish (MSG_NORMAL, " type: %s\n", ref->attr->type_name);
message_publish (MSG_NORMAL, " value: %s\n", print_val().c_str());
message_publish (MSG_NORMAL, "--====================================--\n");
}
static void print_qual(NODE *n)
{
if (n == NULL)
return;
printf(" where ");
if (n->kind == N_SELECT) {
print_qualattr(n->u.SELECT.selattr);
print_op(n->u.SELECT.op);
print_val(n->u.SELECT.value);
} else {
print_qualattr(n->u.JOIN.joinattr1);
print_op(n->u.JOIN.op);
printf(" ");
print_qualattr(n->u.JOIN.joinattr2);
}
}
int
main(int argc, char *argv[])
{
int ret;
MFS_Stat_t stat;
ret = MFS_Init("mumble-28.cs.wisc.edu", 5011);
print_val(ret);
ret = MFS_Lookup(0, "test");
print_val(ret);
ret = MFS_Stat(0, &stat);
print_val(ret);
ret = MFS_Write(0, (char*) &buffer, 1);
print_val(ret);
ret = MFS_Read(0, (char*) &buffer, 14);
print_val(ret);
ret = MFS_Creat(0, MFS_DIRECTORY, "test_filename");
print_val(ret);
ret = MFS_Unlink(0, "test_filename");
print_val(ret);
ret = MFS_Shutdown();
print_val(ret);
return 0;
}
static void print_conf(void) {
warning("\n");
warning("######################## ASMCHO CONFIGURATION ########################\n\n");
print_val("source\t: %s", sfile);
switch (dst_flag) {
case DST_STDOUT :
print_val("destination\t: stdout");
break;
case DST_STDERR :
print_val("destination\t: stderr");
break;
case DST_FILE :
default:
print_val("destination\t: %s", dfile);
break;
}
if (lst_flag > 0) {
print_val("list file\t: %s", lst_file);
} else {
print_val("list file\t: no output");
}
switch (output_type) {
case OFMT_BIN :
print_val("output_type\t: binary format (executable by simulator)");
break;
case OFMT_STR_BIN :
print_val("output_type\t: binary string format");
break;
case OFMT_STR_HEX :
print_val("output_type\t: hexadecimal string format");
break;
case OFMT_COE :
print_val("output_type\t: coe format");
break;
case OFMT_EX_MNE :
print_val("output_type\t: assembly after expand mnemonic");
break;
default :
print_val("print_conf: unexpected output_type");
exit(1);
break;
}
print_val("output_line_min\t: %d", output_line_min);
switch (arch_type) {
case ARCH_OCORE :
print_val("architecture\t: ocore");
break;
case ARCH_POCORE :
print_val("architecture\t: pocore");
break;
default :
print_val("print_conf: unexpected arch_type");
break;
}
warning("\n######################################################################\n\n");
}
/*
* Fill in the buffer pointed to by h with a tar format header. This buffer
* must always have space for 512 characters, which is a requirement by
* the tar format.
*/
void
tarCreateHeader(char *h, const char *filename, const char *linktarget,
size_t size, mode_t mode, uid_t uid, gid_t gid, time_t mtime)
{
/*
* Note: most of the fields in a tar header are not supposed to be
* null-terminated. We use sprintf, which will write a null after the
* required bytes; that null goes into the first byte of the next field.
* This is okay as long as we fill the fields in order.
*/
memset(h, 0, 512); /* assume tar header size */
/* Name 100 */
sprintf(&h[0], "%.99s", filename);
if (linktarget != NULL || S_ISDIR(mode))
{
/*
* We only support symbolic links to directories, and this is
* indicated in the tar format by adding a slash at the end of the
* name, the same as for regular directories.
*/
int flen = strlen(filename);
flen = Min(flen, 99);
h[flen] = '/';
h[flen + 1] = '\0';
}
/* Mode 8 */
sprintf(&h[100], "%07o ", (int) mode);
/* User ID 8 */
sprintf(&h[108], "%07o ", (int) uid);
/* Group 8 */
sprintf(&h[116], "%07o ", (int) gid);
/* File size 12 - 11 digits, 1 space; use print_val for 64 bit support */
if (linktarget != NULL || S_ISDIR(mode))
/* Symbolic link or directory has size zero */
print_val(&h[124], 0, 8, 11);
else
print_val(&h[124], size, 8, 11);
sprintf(&h[135], " ");
/* Mod Time 12 */
sprintf(&h[136], "%011o ", (int) mtime);
/* Checksum 8 cannot be calculated until we've filled all other fields */
if (linktarget != NULL)
{
/* Type - Symbolic link */
sprintf(&h[156], "2");
/* Link Name 100 */
sprintf(&h[157], "%.99s", linktarget);
}
else if (S_ISDIR(mode))
/* Type - directory */
sprintf(&h[156], "5");
else
/* Type - regular file */
sprintf(&h[156], "0");
/* Magic 6 */
sprintf(&h[257], "ustar");
/* Version 2 */
sprintf(&h[263], "00");
/* User 32 */
/* XXX: Do we need to care about setting correct username? */
sprintf(&h[265], "%.31s", "postgres");
/* Group 32 */
/* XXX: Do we need to care about setting correct group name? */
sprintf(&h[297], "%.31s", "postgres");
/* Major Dev 8 */
sprintf(&h[329], "%07o ", 0);
/* Minor Dev 8 */
sprintf(&h[337], "%07o ", 0);
/* Prefix 155 - not used, leave as nulls */
/*
* We mustn't overwrite the next field while inserting the checksum.
* Fortunately, the checksum can't exceed 6 octal digits, so we just write
* 6 digits, a space, and a null, which is legal per POSIX.
*/
sprintf(&h[148], "%06o ", tarChecksum(h));
}
/******************************************************************************
main
*****************************************************************************/
int
main( int pargc, char* pargv[] )
{
val_t val;
map_init();
if ( pargc == 1) {
char *cmd;
char* cmds = cmd;
int cmdlen = 0;
cmd[0] = 0;
printf("Use Control-C to quit.\n");
for( ;; ) {
top:
// print command line.
printf( "\r> %s", cmd );
cmdlen = strlen(cmd);
for( ;; ) {
char c = getchar();
if ( c == '\b' ) {
if ( cmdlen > 0 ) {
cmd[--cmdlen] = 0;
printf( "\r> %s \b", cmd );
}
} else if ( c == '\r' ) {
putc('\n', stdout);
break;
} else if ( c == 3 ) {
printf("QUIT\n");
exit(0);
} else if ( cmdlen < sizeof(cmd)-1 ) {
putc(c, stdout);
//printf("%d\n", c);
cmd[cmdlen++] = c;
cmd[cmdlen] = 0;
}
}
reset( 1, &cmds );
/* parse the expression. */
if ( parse( &val ) ) {
/* print the value. */
print_val( &val );
} else {
printf("Error.\n");
}
}
}
reset( pargc - 1, pargv + 1 );
/* parse the expression. */
parse_expr( &val );
/* print the value. */
print_val( &val );
map_clear();
return 0;
}
void _print_ir(uint32_t ir, FILE *fp) {
uint8_t opcode,funct;
const char *name;
/*
union {
uint32_t i;
float f;
} a, b, c;
*/
fprintf(fp, "%4lx.[%4x] ", cnt, pc);
opcode = get_opcode(ir);
funct = get_funct(ir);
switch (opcode) {
case SPECIAL :
name = SFunctMap[funct];
break;
case IO :
name = IOFunctMap[funct];
break;
case FPI :
name = FFunctMap[funct];
break;
default:
name = InstMap[opcode];
break;
}
switch (opcode) {
case SPECIAL :
switch (funct) {
case ADD_F : case SUB_F : case MUL_F : case NOR_F :
case AND_F : case OR_F : case SLL_F : case SRL_F :
print_val(iggg, get_rdi(ir), _GRD, get_rsi(ir), _GRS, get_rti(ir), _GRT);
break;
case CALLR_F : case B_F :
print_val(ig, get_rsi(ir), _GRS);
break;
case FLD_F : case FST_F :
print_val(ifgg, get_rdi(ir), _GRD, get_rsi(ir), _GRS, get_rti(ir), _GRT);
break;
case HALT_F :
print_val(i);
break;
default :
unknown_ir();
break;
}
break;
case IO :
switch (funct) {
case INPUT_F :
print_val(ig, get_rdi(ir), _GRD);
break;
case OUTPUT_F :
print_val(ig, get_rsi(ir), _GRS);
break;
default :
unknown_ir();
break;
}
break;
case FPI :
switch (funct) {
case FADD_F: case FSUB_F: case FMUL_F: case FDIV_F:
print_val(ifff, get_rdi(ir), _FRD, get_rsi(ir), _FRS, get_rti(ir), _FRT);
break;
case FSQRT_F: case FABS_F: case FMOV_F: case FNEG_F:
print_val(iff, get_rdi(ir), _FRD, get_rsi(ir), _FRS);
break;
default :
unknown_ir();
break;
}
break;
case ADDI: case SUBI: case MULI: case SLLI:
case SRLI: case LDI: case STI:
print_val(iggi, get_rsi(ir), _GRS, get_rti(ir), _GRT, _IMM);
break;
case JMP: case CALL:
print_val(il, get_target(ir));
break;
case MVLO: case MVHI:
print_val(igi, get_rsi(ir), _GRS, _IMM);
break;
case JEQ: case JNE: case JLT: case JLE:
print_val(iggl, get_rsi(ir), _GRS, get_rti(ir), _GRT, _IMM);
break;
case LD: case ST:
print_val(iggg, get_rdi(ir), _GRD, get_rsi(ir), _GRS, get_rti(ir), _GRT);
break;
case RETURN :
print_val(i);
break;
case FLDI: case FSTI:
print_val(ifgi, get_rti(ir), _FRT, get_rsi(ir), _GRS, _IMM);
break;
case FJEQ: case FJLT:
print_val(iffl, get_rsi(ir), _FRS, get_rti(ir), _GRT, _IMM);
break;
default :
unknown_ir();
break;
}
}
void main ()
{
err_t err;
reg_t regs [REG_MAX];
context_t * context;
char_t token [TOKEN_LEN_MAX];
byte_t len;
context = (context_t *) regs;
// Startup banner
print_char ('P');
print_char ('T');
print_char ('1');
print_char ('.');
print_char ('1');
print_char (13); // carriage return
print_char (10); // new line
while (1)
{
err = scan_token (token, &len);
if (err == E_OK)
{
if (!len) break;
switch (token [0])
{
case 'R':
if (len != 2)
{
err = E_LEN;
break;
}
err = reg_read (regs, token [1]);
print_val (context->val);
break;
case 'W':
if (len != 2)
{
err = E_LEN;
break;
}
err = reg_write (regs, token [1]);
break;
case 'X':
if (len != 2)
{
err = E_LEN;
break;
}
err = sub_exec (regs, token [1]);
break;
default:
if (len > 4)
{
err = E_LEN;
break;
}
err = val_write (regs, token, len);
}
}
print_stat (err);
}
}
static void ddr_ram_setup(void)
{
uint8_t b, c, bank, ma;
uint16_t i;
unsigned long bank_address;
print_debug("CN400 RAM init starting\n");
pci_write_config8(ctrl.d0f7, 0x75, 0x08);
/* No Interleaving or Multi Page */
pci_write_config8(ctrl.d0f3, 0x69, 0x00);
pci_write_config8(ctrl.d0f3, 0x6b, 0x10);
/*
DRAM MA Map Type Device 0 Fn3 Offset 50-51
Determine memory addressing based on the module's memory technology and
arrangement. See Table 4-9 of Intel's 82443GX datasheet for details.
Bank 1/0 MA map type 50[7-5]
Bank 1/0 command rate 50[4]
Bank 3/2 MA map type 50[3-1]
Bank 3/2 command rate 50[0]
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0;
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
//print_val("Detecting Memory\nNumber of Banks ",b);
// Only supporting 4 bank chips just now
if( b == 4 ){
/* Read SPD byte 3, Number of row addresses. */
c = 0x01;
bank = 0x40;
b = smbus_read_byte(DIMM0, SPD_NUM_ROWS);
//print_val("\nNumber of Rows ", b);
if( b >= 0x0d ){ // 256/512Mb
if (b == 0x0e)
bank = 0x48;
else
bank = 0x44;
/* Read SPD byte 13, Primary DRAM width. */
b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
//print_val("\nPrimary DRAM width", b);
if( b != 4 ) // not 64/128Mb (x4)
c = 0x81; // 256Mb
}
/* Read SPD byte 4, Number of column addresses. */
b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS);
//print_val("\nNo Columns ",b);
if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr
if( b == 9 ) c |= 0x40; // 9 bit col addr
if( b == 8 ) c |= 0x20; // 8 bit col addr
//print_val("\nMA type ", c);
pci_write_config8(ctrl.d0f3, 0x50, c);
}
/* Disable Upper Banks */
pci_write_config8(ctrl.d0f3, 0x51, 0x00);
/* else
{
die("DRAM module size is not supported by CN400\n");
}
*/
/*
DRAM bank size. See 4.3.1 pg 35
5a->5d set to end address for each bank. 1 bit == 32MB
5a = bank 0
5b = bank 0 + b1
5c = bank 0 + b1 + b2
5d = bank 0 + b1 + b2 + b3
*/
// Read SPD byte 31 Module bank density
//c = 0;
b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
if( b & 0x02 )
{
c = 0x40; // 2GB
bank |= 0x02;
}
else if( b & 0x01)
{
c = 0x20; // 1GB
if (bank == 0x48) bank |= 0x01;
else bank |= 0x03;
}
else if( b & 0x80)
{
c = 0x10; // 512MB
if (bank == 0x44) bank |= 0x02;
}
else if( b & 0x40)
{
c = 0x08; // 256MB
if (bank == 0x44) bank |= 0x01;
else bank |= 0x03;
}
else if( b & 0x20)
{
c = 0x04; // 128MB
if (bank == 0x40) bank |= 0x02;
}
else if( b & 0x10)
{
c = 0x02; // 64MB
bank |= 0x01;
}
else if( b & 0x08) c = 0x01; // 32MB
else c = 0x01; // Error, use default
// set bank zero size
pci_write_config8(ctrl.d0f3, 0x40, c);
// SPD byte 5 # of physical banks
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS);
//print_val("\nNo Physical Banks ",b);
if( b == 2)
{
c <<=1;
bank |= 0x80;
}
/* else
{
die("Only a single DIMM is supported by EPIA-N(L)\n");
}
*/
// set banks 1,2,3...
pci_write_config8(ctrl.d0f3, 0x41,c);
pci_write_config8(ctrl.d0f3, 0x42,c);
pci_write_config8(ctrl.d0f3, 0x43,c);
pci_write_config8(ctrl.d0f3, 0x44,c);
pci_write_config8(ctrl.d0f3, 0x45,c);
pci_write_config8(ctrl.d0f3, 0x46,c);
pci_write_config8(ctrl.d0f3, 0x47,c);
/* Top Rank Address Mirrored to the South Bridge */
/* over the VLink */
pci_write_config8(ctrl.d0f7, 0x57, (c << 1));
ma = bank;
/* Read SPD byte 18 CAS Latency */
b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES);
/* print_debug("\nCAS Supported ");
if(b & 0x04)
print_debug("2 ");
if(b & 0x08)
print_debug("2.5 ");
if(b & 0x10)
print_debug("3");
c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
print_val("\nCycle time at CL X (nS)", c);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND);
print_val("\nCycle time at CL X-0.5 (nS)", c);
c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
print_val("\nCycle time at CL X-1 (nS)", c);
*/
/* Scaling of Cycle Time SPD data */
/* 7 4 3 0 */
/* ns x0.1ns */
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if( b & 0x10 ){ // DDR offering optional CAS 3
//print_debug("\nStarting at CAS 3");
c = 0x30;
/* see if we can better it */
if( b & 0x08 ){ // DDR mandatory CAS 2.5
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5
//print_debug("\nWe can do CAS 2.5");
c = 0x20;
}
}
if( b & 0x04 ){ // DDR mandatory CAS 2
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}else{ // no optional CAS values just 2 & 2.5
//print_debug("\nStarting at CAS 2.5");
c = 0x20; // assume CAS 2.5
if( b & 0x04){ // Should always happen
if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
//print_debug("\nWe can do CAS 2");
c = 0x10;
}
}
}
/* Scale DRAM Cycle Time to tRP/tRCD */
/* 7 2 1 0 */
/* ns x0.25ns */
if ( bank <= 0x50 ) bank = 0x14;
else if (bank <= 0x60) bank = 0x18;
else bank = 0x1E;
/*
DRAM Timing Device 0 Fn 3 Offset 56
RAS Pulse width 56[7,6]
CAS Latency 56[5,4]
Row pre-charge 56[1,0]
SDR DDR
00 1T -
01 2T 2T
10 3T 2.5T
11 - 3T
RAS/CAS delay 56[3,2]
Determine row pre-charge time (tRP)
Read SPD byte 27, min row pre-charge time.
*/
b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME);
//print_val("\ntRP ",b);
if ( b >= (5 * bank)) {
c |= 0x03; // set tRP = 5T
}
else if ( b >= (4 * bank)) {
c |= 0x02; // set tRP = 4T
}
else if ( b >= (3 * bank)) {
c |= 0x01; // set tRP = 3T
}
/*
Determine RAS to CAS delay (tRCD)
Read SPD byte 29, min row pre-charge time.
*/
b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY);
//print_val("\ntRCD ",b);
if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T
else if ( b >= (4 * bank)) c |= 0x08; // set tRCD = 4T
else if ( b >= (3 * bank)) c |= 0x04; // set tRCD = 3T
/*
Determine RAS pulse width (tRAS)
Read SPD byte 30, device min active to pre-charge time.
*/
/* tRAS is in whole ns */
bank = bank >> 2;
b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
//print_val("\ntRAS ",b);
//print_val("\nBank ", bank);
if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T
else if ( b >= (8 * bank)) c |= 0x80; // set tRAS = 8T
else if ( b >= (7 * bank)) c |= 0x40; // set tRAS = 7T
/* Write DRAM Timing All Banks I */
pci_write_config8(ctrl.d0f3, 0x56, c);
/* TWrite DRAM Timing All Banks II */
pci_write_config8(ctrl.d0f3, 0x57, 0x1a);
/* DRAM arbitration timer */
pci_write_config8(ctrl.d0f3, 0x65, 0x99);
/*
DRAM Clock Device 0 Fn 3 Offset 68
*/
bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
/* Setup DRAM Cycle Time */
if ( bank <= 0x50 )
{
/* DRAM DDR Control Alert! Alert! See also c3_cpu_setup */
/* This sets to 133MHz FSB / DDR400. */
pci_write_config8(ctrl.d0f3, 0x68, 0x85);
}
else if (bank <= 0x60)
{
/* DRAM DDR Control Alert! Alert! This hardwires to */
/* 133MHz FSB / DDR333. See also c3_cpu_setup */
pci_write_config8(ctrl.d0f3, 0x68, 0x81);
}
else
{
/* DRAM DDR Control Alert! Alert! This hardwires to */
/* 133MHz FSB / DDR266. See also c3_cpu_setup */
pci_write_config8(ctrl.d0f3, 0x68, 0x80);
}
/* Delay >= 100ns after DRAM Frequency adjust, See 4.1.1.3 pg 15 */
udelay(200);
/*
Determine bank interleave
Read SPD byte 17, Number of banks on SDRAM device.
*/
c = 0x0F;
b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM);
if( b == 4) c |= 0x80;
else if (b == 2) c |= 0x40;
/* 4-Way Interleave With Multi-Paging (From Running System)*/
pci_write_config8(ctrl.d0f3, 0x69, c);
/*DRAM Controller Internal Options */
pci_write_config8(ctrl.d0f3, 0x54, 0x01);
/* DRAM Arbitration Control */
pci_write_config8(ctrl.d0f3, 0x66, 0x82);
/* DRAM Control */
pci_write_config8(ctrl.d0f3, 0x6e, 0x80);
/* Disable refresh for now */
pci_write_config8(ctrl.d0f3, 0x6a, 0x00);
/* DDR Clock Gen Duty Cycle Control */
pci_write_config8(ctrl.d0f3, 0xEE, 0x01);
/* DRAM Clock Control */
pci_write_config8(ctrl.d0f3, 0x6c, 0x00);
/* DRAM Bus Turn-Around Setting */
pci_write_config8(ctrl.d0f3, 0x60, 0x01);
/* Disable DRAM refresh */
pci_write_config8(ctrl.d0f3,0x6a,0x0);
/* Memory Pads Driving and Range Select */
pci_write_config8(ctrl.d0f3, 0xe2, 0xAA);
pci_write_config8(ctrl.d0f3, 0xe3, 0x00);
pci_write_config8(ctrl.d0f3, 0xe4, 0x99);
/* DRAM signal timing control */
pci_write_config8(ctrl.d0f3, 0x74, 0x99);
pci_write_config8(ctrl.d0f3, 0x76, 0x09);
pci_write_config8(ctrl.d0f3, 0x77, 0x12);
pci_write_config8(ctrl.d0f3, 0xe0, 0xAA);
pci_write_config8(ctrl.d0f3, 0xe1, 0x00);
pci_write_config8(ctrl.d0f3, 0xe6, 0x00);
pci_write_config8(ctrl.d0f3, 0xe8, 0xEE);
pci_write_config8(ctrl.d0f3, 0xea, 0xEE);
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
c = b | 0x40;
pci_write_config8(ctrl.d0f3, 0xb0, c);
/* Set RAM Decode method */
pci_write_config8(ctrl.d0f3, 0x55, 0x0a);
/* Enable DIMM Ranks */
pci_write_config8(ctrl.d0f3, 0x48, ma);
udelay(200);
c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS);
c &= 0x08;
if ( c == 0x08 )
{
print_debug("Setting Burst Length 8\n");
/*
CPU Frequency Device 0 Function 2 Offset 54
CPU FSB Operating Frequency (bits 7:5)
000 : 100MHz 001 : 133MHz
010 : 200MHz
011->111 : Reserved
SDRAM BL8 (4)
Don't change Frequency from power up defaults
This seems to lockup the RAM interface
*/
c = pci_read_config8(ctrl.d0f2, 0x54);
c |= 0x10;
pci_write_config8(ctrl.d0f2, 0x54, c);
i = 0x008; // Used later to set SDRAM MSR
}
for( bank = 0 , bank_address=0; bank <= b ; bank++) {
/*
DDR init described in Via VT8623 BIOS Porting Guide. Pg 28 (4.2.3.1)
*/
/* NOP command enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_NOP;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* read a double word from any address of the dimm */
dimm_read(bank_address,0x1f000);
//udelay(200);
/* All bank precharge Command Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_PRECHARGE;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
dimm_read(bank_address,0x1f000);
/* MSR Enable Low DIMM*/
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_MSR_LOW;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* TODO: Bank Addressing for Different Numbers of Row Addresses */
dimm_read(bank_address,0x2000);
udelay(1);
dimm_read(bank_address,0x800);
udelay(1);
/* All banks precharge Command Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_PRECHARGE;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
dimm_read(bank_address,0x1f200);
/* CBR Cycle Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_CBR;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/* Read 8 times */
for (c=0;c<8;c++) {
dimm_read(bank_address,0x1f300);
udelay(100);
}
/* MSR Enable */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_MSR_LOW;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
/*
Mode Register Definition
with adjustement so that address calculation is correct - 64 bit technology, therefore
a0-a2 refer to byte within a 64 bit long word, and a3 is the first address line presented
to DIMM as a row or column address.
MR[9-7] CAS Latency
MR[6] Burst Type 0 = sequential, 1 = interleaved
MR[5-3] burst length 001 = 2, 010 = 4, 011 = 8, others reserved
MR[0-2] dont care
CAS Latency
000 reserved
001 reserved
010 2
011 3
100 reserved
101 1.5
110 2.5
111 reserved
CAS 2 0101011000 = 0x158
CAS 2.5 1101011000 = 0x358
CAS 3 0111011000 = 0x1d8
*/
c = pci_read_config8(ctrl.d0f3, 0x56);
if( (c & 0x30) == 0x10 )
dimm_read(bank_address,(0x150 + i));
else if((c & 0x30) == 0x20 )
dimm_read(bank_address,(0x350 + i));
else
dimm_read(bank_address,(0x1d0 + i));
/* Normal SDRAM Mode */
c = pci_read_config8(ctrl.d0f3, DRAM_MISC_CTL);
c &= 0xf8; /* Clear bits 2-0. */
c |= RAM_COMMAND_NORMAL;
pci_write_config8(ctrl.d0f3, DRAM_MISC_CTL, c);
bank_address = pci_read_config8(ctrl.d0f3,0x40+bank) * 0x2000000;
} // end of for each bank
/* Set DRAM DQS Output Control */
pci_write_config8(ctrl.d0f3, 0x79, 0x11);
/* Set DQS A/B Input delay to defaults */
pci_write_config8(ctrl.d0f3, 0x7A, 0xA1);
pci_write_config8(ctrl.d0f3, 0x7B, 0x62);
/* DQS Duty Cycle Control */
pci_write_config8(ctrl.d0f3, 0xED, 0x11);
/* SPD byte 5 # of physical banks */
b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1;
/* determine low bond */
if( b == 2)
bank_address = pci_read_config8(ctrl.d0f3,0x40) * 0x2000000;
else
bank_address = 0;
for(i = 0x30 ; i < 0x0ff; i++){
pci_write_config8(ctrl.d0f3,0x70,i);
// clear
*(volatile unsigned long*)(0x4000) = 0;
*(volatile unsigned long*)(0x4100+bank_address) = 0;
*(volatile unsigned long*)(0x4200) = 0;
*(volatile unsigned long*)(0x4300+bank_address) = 0;
*(volatile unsigned long*)(0x4400) = 0;
*(volatile unsigned long*)(0x4500+bank_address) = 0;
// fill
*(volatile unsigned long*)(0x4000) = 0x12345678;
*(volatile unsigned long*)(0x4100+bank_address) = 0x81234567;
*(volatile unsigned long*)(0x4200) = 0x78123456;
*(volatile unsigned long*)(0x4300+bank_address) = 0x67812345;
*(volatile unsigned long*)(0x4400) = 0x56781234;
*(volatile unsigned long*)(0x4500+bank_address) = 0x45678123;
// verify
if( *(volatile unsigned long*)(0x4000) != 0x12345678)
continue;
if( *(volatile unsigned long*)(0x4100+bank_address) != 0x81234567)
continue;
if( *(volatile unsigned long*)(0x4200) != 0x78123456)
continue;
if( *(volatile unsigned long*)(0x4300+bank_address) != 0x67812345)
continue;
if( *(volatile unsigned long*)(0x4400) != 0x56781234)
continue;
if( *(volatile unsigned long*)(0x4500+bank_address) != 0x45678123)
continue;
// if everything verified then found low bond
break;
}
print_val("\nLow Bond ",i);
if( i < 0xff ){
c = i++;
for( ; i <0xff ; i++){
pci_write_config8(ctrl.d0f3,0x70, i);
// clear
*(volatile unsigned long*)(0x8000) = 0;
*(volatile unsigned long*)(0x8100+bank_address) = 0;
*(volatile unsigned long*)(0x8200) = 0x0;
*(volatile unsigned long*)(0x8300+bank_address) = 0;
*(volatile unsigned long*)(0x8400) = 0x0;
*(volatile unsigned long*)(0x8500+bank_address) = 0;
// fill
*(volatile unsigned long*)(0x8000) = 0x12345678;
*(volatile unsigned long*)(0x8100+bank_address) = 0x81234567;
*(volatile unsigned long*)(0x8200) = 0x78123456;
*(volatile unsigned long*)(0x8300+bank_address) = 0x67812345;
*(volatile unsigned long*)(0x8400) = 0x56781234;
*(volatile unsigned long*)(0x8500+bank_address) = 0x45678123;
// verify
if( *(volatile unsigned long*)(0x8000) != 0x12345678)
break;
if( *(volatile unsigned long*)(0x8100+bank_address) != 0x81234567)
break;
if( *(volatile unsigned long*)(0x8200) != 0x78123456)
break;
if( *(volatile unsigned long*)(0x8300+bank_address) != 0x67812345)
break;
if( *(volatile unsigned long*)(0x8400) != 0x56781234)
break;
if( *(volatile unsigned long*)(0x8500+bank_address) != 0x45678123)
break;
}
print_val(" High Bond ",i);
c = ((i - c)<<1)/3 + c;
print_val(" Setting DQS delay",c);
print_debug("\n");
pci_write_config8(ctrl.d0f3,0x70,c);
}else{
pci_write_config8(ctrl.d0f3,0x70,0x67);
}
/* Set DQS ChA Data Output Delay to the default */
pci_write_config8(ctrl.d0f3, 0x71, 0x65);
/* Set Ch B DQS Output Delays */
pci_write_config8(ctrl.d0f3, 0x72, 0x2a);
pci_write_config8(ctrl.d0f3, 0x73, 0x29);
pci_write_config8(ctrl.d0f3, 0x78, 0x03);
/* Mystery Value */
pci_write_config8(ctrl.d0f3, 0x67, 0x50);
/* Enable Toggle Limiting */
pci_write_config8(ctrl.d0f4, 0xA3, 0x80);
/*
DRAM refresh rate Device 0 F3 Offset 6a
TODO :: Fix for different DRAM technologies
other than 512Mb and DRAM Freq
Units of 16 DRAM clock cycles - 1.
*/
//c = pci_read_config8(ctrl.d0f3, 0x68);
//c &= 0x07;
//b = smbus_read_byte(DIMM0, SPD_REFRESH);
//print_val("SPD_REFRESH = ", b);
pci_write_config8(ctrl.d0f3,0x6a,0x65);
/* SMM and APIC decoding, we do not use SMM */
b = 0x29;
pci_write_config8(ctrl.d0f3, 0x86, b);
/* SMM and APIC decoding mirror */
pci_write_config8(ctrl.d0f7, 0xe6, b);
/* Open Up the Rest of the Shadow RAM */
pci_write_config8(ctrl.d0f3,0x80,0xff);
pci_write_config8(ctrl.d0f3,0x81,0xff);
/* pci */
pci_write_config8(ctrl.d0f7,0x70,0x82);
pci_write_config8(ctrl.d0f7,0x73,0x01);
pci_write_config8(ctrl.d0f7,0x76,0x50);
pci_write_config8(ctrl.d0f7,0x71,0xc8);
/* VGA device. */
pci_write_config16(ctrl.d0f3, 0xa0, (1 << 15));
pci_write_config16(ctrl.d0f3, 0xa4, 0x0010);
print_debug("CN400 raminit.c done\n");
}
enumError cmd_test_options()
{
printf("Options (hex=dec):\n");
printf(" test: %16d\n",testmode);
printf(" verbose: %16d\n",verbose);
printf(" width: %16d\n",opt_width);
#if IS_WWT
print_val( "size:", opt_size, 0);
print_val( "hd sec-size:", opt_hss, 0);
print_val( "wb sec-size:", opt_wss, 0);
print_val( "repair-mode:", repair_mode, 0);
#elif defined(TEST)
u64 opt_size = 0;
#endif
snprintf(iobuf,sizeof(iobuf)," = %s",oft_info[output_file_type].name);
print_val( "output-mode:", output_file_type, iobuf );
SetupOptionsWDF();
if ( opt_wdf_version || opt_wdf_align || opt_wdf_min_holesize )
{
if ( use_wdf_version != opt_wdf_version )
snprintf(iobuf,sizeof(iobuf)," => use v%d",use_wdf_version);
else
*iobuf = 0;
print_val( "wdf-version:", opt_wdf_version, iobuf );
if ( use_wdf_align != opt_wdf_align )
snprintf(iobuf,sizeof(iobuf)," => use %x (%s)",
use_wdf_align, wd_print_size_1024(0,0,use_wdf_align,false) );
else
*iobuf = 0;
print_val( "align-wdf:", opt_wdf_align, iobuf );
print_val( "minhole-wdf", opt_wdf_min_holesize, 0 );
}
print_val( "chunk-mode:", opt_chunk_mode, 0 );
print_val( "chunk-size:", opt_chunk_size, force_chunk_size ? " FORCE!" : "" );
print_val( "max-chunks:", opt_max_chunks, 0 );
#ifdef TEST
{
u64 filesize[] = { 100ull*MiB, 1ull*GiB, 10ull*GiB, opt_size, 0 };
u64 *fs_ptr = filesize;
for (;;)
{
u32 n_blocks;
u32 block_size = CalcBlockSizeCISO(&n_blocks,*fs_ptr);
printf(" CISO block size %12llx = %12lld -> %5u * %8x/hex == %12llx/hex\n",
*fs_ptr, *fs_ptr, n_blocks, block_size,
(u64)block_size * n_blocks );
if (!*++fs_ptr)
break;
}
}
#endif
printf(" auto-split: %16x = %12d\n",opt_auto_split,opt_auto_split);
printf(" split: %16x = %12d\n",opt_split,opt_split);
print_val( "split-size:", opt_split_size, 0 );
printf(" compression: %16x = %12d = %s (level=%d)\n",
opt_compr_method, opt_compr_method,
wd_get_compression_name(opt_compr_method,"?"), opt_compr_level );
printf(" level: %16x = %12d\n",opt_compr_level,opt_compr_level);
print_val( " chunk-size:", opt_compr_chunk_size, 0 );
print_val( "mem:", opt_mem, 0 );
GetMemLimit();
print_val( "mem limit:", opt_mem, 0 );
printf(" escape-char: %16x = %12d\n",escape_char,escape_char);
printf(" print-time: %16x = %12d\n",opt_print_time,opt_print_time);
printf(" sort-mode: %16x = %12d\n",sort_mode,sort_mode);
printf(" show-mode: %16x = %12d\n",opt_show_mode,opt_show_mode);
printf(" unit: %16x = %12d, unit=%s\n",
opt_unit, opt_unit, wd_get_size_unit(opt_unit,"?") );
printf(" limit: %16x = %12d\n",opt_limit,opt_limit);
#if IS_WIT
printf(" file-limit: %16x = %12d\n",opt_file_limit,opt_file_limit);
printf(" block-size: %16x = %12d\n",opt_block_size,opt_block_size);
#endif
printf(" gcz-block: %16x = %12d\n",opt_gcz_block_size,opt_gcz_block_size);
printf(" rdepth: %16x = %12d\n",opt_recurse_depth,opt_recurse_depth);
printf(" enc: %16x = %12d\n",encoding,encoding);
printf(" region: %16x = %12d\n",opt_region,opt_region);
printf(" prealloc: %16x = %12d\n",prealloc_mode,prealloc_mode);
if (opt_ios_valid)
{
const u32 hi = opt_ios >> 32;
const u32 lo = (u32)opt_ios;
if ( hi == 1 && lo < 0x100 )
printf(" ios: %08x-%08x = IOS %u\n", hi, lo, lo );
else
printf(" ios: %08x-%08x\n", hi, lo );
}
printf(" modify: %16x = %12d\n",opt_modify,opt_modify);
if (modify_name)
printf(" modify name: '%s'\n",modify_name);
if (modify_id)
printf(" modify id: '%s'\n",modify_id);
if (modify_disc_id)
printf(" modify disc id: '%s'\n",modify_disc_id);
if (modify_boot_id)
printf(" modify boot id: '%s'\n",modify_boot_id);
if (modify_ticket_id)
printf(" modify ticket id: '%s'\n",modify_ticket_id);
if (modify_tmd_id)
printf(" modify tmd id: '%s'\n",modify_tmd_id);
if (modify_wbfs_id)
printf(" modify wbfs id: '%s'\n",modify_wbfs_id);
if ( opt_http || opt_domain )
{
printf(" http: %s\n", opt_http ? "enabled" : "disabled" );
printf(" domain: '%s'\n",opt_domain);
}
#if IS_WWT
char buf_set_time[20];
if (opt_set_time)
{
struct tm * tm = localtime(&opt_set_time);
strftime(buf_set_time,sizeof(buf_set_time),"%F %T",tm);
}
else
strcpy(buf_set_time,"NULL");
printf(" set-time: %16llx = %12lld = %s\n",
(u64)opt_set_time, (u64)opt_set_time,buf_set_time );
#endif
printf(" trim: %16x = %12u\n",opt_trim,opt_trim);
print_val( "align #1:", opt_align1, 0 );
print_val( "align #2:", opt_align2, 0 );
print_val( "align #3:", opt_align3, 0 );
print_val( "align-part:", opt_align_part, 0 );
print_val( "disc-size:", opt_disc_size, 0 );
printf(" partition selector:\n");
wd_print_select(stdout,6,&part_selector);
return ERR_OK;
}
int
p7_gmxb_Dump(FILE *ofp, P7_GMXB *gxb, int flags)
{
int g, i, k, x;
int *bnd_ip = gxb->bnd->imem;
int *bnd_kp = gxb->bnd->kmem;
float *dp = gxb->dp;
float *xp = gxb->xmx;
int M = gxb->bnd->M;
int ia, ib;
int ka, kb;
int width = 9;
int precision = 4;
/* Header */
fprintf(ofp, " ");
for (k = 0; k <= M; k++) fprintf(ofp, "%*d ", width, k);
if (! (flags & p7_HIDE_SPECIALS)) fprintf(ofp, "%*s %*s %*s %*s %*s\n", width, "E", width, "N", width, "J", width, "B", width, "C");
fprintf(ofp, " ");
for (k = 0; k <= M; k++) fprintf(ofp, "%*.*s ", width, width, "----------");
if (! (flags & p7_HIDE_SPECIALS)) fprintf(ofp, "%*.*s ", width, width, "----------");
fprintf(ofp, "\n");
i = 0;
for (g = 0; g < gxb->bnd->nseg; g++)
{
ia = *bnd_ip;
bnd_ip++;
ib = *bnd_ip;
bnd_ip++;
if (ia > i+1) fprintf(ofp, "...\n\n");
for (i = ia; i <= ib; i++)
{
ka = *bnd_kp;
bnd_kp++;
kb = *bnd_kp;
bnd_kp++;
/* match cells */
fprintf(ofp, "%3d M ", i);
for (k = 0; k < ka; k++) fprintf (ofp, "%*s ", width, ".....");
for ( ; k <= kb; k++) print_val(ofp, dp[(k-ka)*p7G_NSCELLS + p7G_M], width, precision, flags);
for ( ; k <= M; k++) fprintf (ofp, "%*s ", width, ".....");
/* ENJBC specials */
if (! (flags & p7_HIDE_SPECIALS)) {
for (x = 0; x < p7G_NXCELLS; x++) print_val(ofp, xp[x], width, precision, flags);
}
fprintf(ofp, "\n");
/* insert cells */
fprintf(ofp, "%3d I ", i);
for (k = 0; k < ka; k++) fprintf (ofp, "%*s ", width, ".....");
for ( ; k <= kb; k++) print_val(ofp, dp[(k-ka)*p7G_NSCELLS + p7G_I], width, precision, flags);
for ( ; k <= M; k++) fprintf (ofp, "%*s ", width, ".....");
fprintf(ofp, "\n");
/* delete cells */
fprintf(ofp, "%3d D ", i);
for (k = 0; k < ka; k++) fprintf(ofp, "%*s ", width, ".....");
for ( ; k <= kb; k++) print_val(ofp, dp[(k-ka)*p7G_NSCELLS + p7G_D], width, precision, flags);
for ( ; k <= M; k++) fprintf(ofp, "%*s ", width, ".....");
fprintf(ofp, "\n\n");
dp += p7G_NSCELLS * (kb-ka+1); /* skip ahead to next dp sparse "row" */
xp += p7G_NXCELLS;
}
}
if (i <= gxb->bnd->L) fprintf(ofp, "...\n");
return eslOK;
}
GC_USER_FUNC int main (int argc, char ** argv)
{
#ifdef MEMWATCH
mwInit();
mwDoFlush(1);
#endif // MEMWATCH
ML_START_TIMING(main_time);
GC_init();
//ml_print_gc_stats();
printf("Compiled for "
#if defined(GC_CHERI)
"GC_CHERI"
#elif defined(GC_BOEHM)
"GC_BOEHM"
#elif defined(GC_NONE)
"GC_NONE"
#elif defined(GC_NOCAP)
"GC_NOCAP"
#else
#error "Define one of GC_CHERI, GC_BOEHM, GC_NONE."
#endif // GC_CHERI, GC_BOEHM, GC_NONE
" at %s\n", __TIME__ " " __DATE__);
//GC_CAP const char * filename = GC_cheri_ptr("ml-tmp", sizeof("ml-tmp"));
//lex_read_file(filename);
//const char str[] = "(fn x . ((fn x . x) 3) + x) 2";
//const char str[] = "fn f . (fn g. (f (fn a . (g g) a))) (fn g. (f (fn a . (g g) a)))";
//const char str[] =
//"((fn f . fn n . if n then n * f (n-1) else 1) (fn n . n)) 5";
// factorial:
//const char str[] =
// "((fn f . (fn g. (f (fn a . (g g) a))) (fn g. (f (fn a . (g g) a)))) (fn f . fn n . if n then n * f (n-1) else 1)) 6";
// for the benchmark:
if (argc < 2)
{
printf("Need a program argument\n");
return 1;
}
if (argc < 3)
{
printf("Need a number argument\n");
return 1;
}
printf("Program should be evaluating something to do with the number %s\n", argv[2]);
int num = atoi(argv[2]);
#ifdef GC_CHERI
gc_cheri_grow_heap(num);
#endif
#ifdef GC_BOEHM
GC_set_max_heap_size(num >= 1024 ? 350000*(num/1024) : num >= 256 ? 200000 : 65536);
#endif
/*const char str[] =
"((fn f . (fn g. (f (fn a . (g g) a))) (fn g. (f (fn f . (g g) f)))) (fn f . fn n . if n then n + f (n-1) else 1)) ";
GC_CAP char * str2 = ml_malloc(sizeof(str)+strlen(argv[1]));
cmemcpy(str2, GC_cheri_ptr(str, sizeof(str)), sizeof(str));
cmemcpy(str2+sizeof(str)-1, GC_cheri_ptr(argv[1], strlen(argv[1]+1)), strlen(argv[1]+1));
*/
GC_CAP const char * str2 = GC_cheri_ptr(argv[1], strlen(argv[1])+1);
unsigned long long before = ml_time();
lex_read_string(str2);
printf("program: %s\n\n", (void*)(str2));
/*size_t i;
for (i=0; i<lex_state.max; i++)
{
putchar(((char*)lex_state.file)[i]);
}
GC_CAP token_t * t;
t = lex();
while (t->type != TKEOF)
{
printf("[%d] (tag=%d alloc=%d) %s\n", ((token_t*)t)->type, (int) GC_cheri_gettag(((token_t*)t)->str), (int) GC_IS_GC_ALLOCATED(((token_t*)t)->str), (char*) ((token_t*)t)->str);
GC_malloc(5000);
t = lex();
}
printf("Finished\n");
return 0;*/
parse_init();
GC_CAP expr_t * expr = GC_INVALID_PTR();
GC_STORE_CAP(expr, parse());
printf("AST:\n");
print_ast(expr);
printf("\nDone printing AST\n");
/*printf("collecting loads\n");
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
ml_collect();
printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~done collecting loads\n");
GC_debug_print_region_stats(&GC_state.thread_local_region);*/
GC_CAP val_t * val = GC_INVALID_PTR();
int i;
for (i=0; i<10; i++)
{
GC_STORE_CAP(val, eval(expr, GC_INVALID_PTR()));
}
unsigned long long after = ml_time();
unsigned long long diff = after - before;
printf("eval: ");
if (!PTR_VALID(val))
printf("(invalid");
else
print_val(val);
printf("\n\n");
printf("[plotdata] %s %llu\n", argv[2], (unsigned long long) diff);
#ifdef GC_CHERI
printf("(young) heap size:\n");
printf("[altplotdata] %s %llu\n", argv[2], (unsigned long long) (GC_cheri_getlen(GC_state.thread_local_region.tospace)));
#ifdef GC_GENERATIONAL
printf("old heap size:\n");
printf("[altplotdataold] %s %llu\n", argv[2], (unsigned long long) (GC_cheri_getlen(GC_state.old_generation.tospace)));
#endif // GC_GENERATIONAL
#endif // GC_CHERI
#ifdef GC_BOEHM
printf("[altplotdata] %s %llu\n", argv[2],
(unsigned long long) GC_get_heap_size());
#endif // GC_BOEHM
ML_STOP_TIMING(main_time, "main()");
ml_print_gc_stats();
ml_print_plot_data();
#ifdef MEMWATCH
mwTerm();
#endif // MEMWATCH
return 0;
}
