void psxRcntUpdate() { if ((upse_r3000_cpu_regs.cycle - psxCounters[3].sCycle) >= psxCounters[3].Cycle) { //printf("%d\n",(upse_r3000_cpu_regs.cycle - psxCounters[3].sCycle)- psxCounters[3].Cycle); psxRcntUpd(3); psxHu32(0x1070) |= BFLIP32(1); } if ((upse_r3000_cpu_regs.cycle - psxCounters[0].sCycle) >= psxCounters[0].Cycle) { psxRcntReset(0); } if ((upse_r3000_cpu_regs.cycle - psxCounters[1].sCycle) >= psxCounters[1].Cycle) { psxRcntReset(1); } if ((upse_r3000_cpu_regs.cycle - psxCounters[2].sCycle) >= psxCounters[2].Cycle) { psxRcntReset(2); } psxRcntSet(); }
void psxRcntInit() { s32 i; // rcnt 0. rcnts[0].rate = 1; rcnts[0].irq = 0x10; // rcnt 1. rcnts[1].rate = 1; rcnts[1].irq = 0x20; // rcnt 2. rcnts[2].rate = 1; rcnts[2].irq = 0x40; // rcnt base. rcnts[3].rate = 1; rcnts[3].mode = RcCountToTarget; rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); for( i = 0; i < CounterQuantity; ++i ) { _psxRcntWcount( i, 0 ); } hSyncCount = 0; spuSyncCount = 0; psxRcntSet(); }
void psxRcntInit() { memset(psxCounters, 0, sizeof(psxCounters)); psxCounters[0].rate = 1; psxCounters[0].interrupt = 0x10; psxCounters[1].rate = 1; psxCounters[1].interrupt = 0x20; psxCounters[2].rate = 1; psxCounters[2].interrupt = 64; psxCounters[3].interrupt = 1; psxCounters[3].mode = 0x58; // The VSync counter mode psxCounters[3].target = 1; psxUpdateVSyncRate(); cnts = 4; psxRcntUpd(0); psxRcntUpd(1); psxRcntUpd(2); psxRcntUpd(3); psxRcntSet(); last = 0; }
void psxRcntUpdate(upse_module_instance_t *ins) { upse_psx_counter_state_t *ctrstate = ins->ctrstate; if ((ins->cpustate.cycle - ctrstate->psxCounters[3].sCycle) >= ctrstate->psxCounters[3].Cycle) { psxRcntUpd(ins, 3); psxHu32(ins, 0x1070) |= BFLIP32(1); } if ((ins->cpustate.cycle - ctrstate->psxCounters[0].sCycle) >= ctrstate->psxCounters[0].Cycle) { psxRcntReset(ins, 0); } if ((ins->cpustate.cycle - ctrstate->psxCounters[1].sCycle) >= ctrstate->psxCounters[1].Cycle) { psxRcntReset(ins, 1); } if ((ins->cpustate.cycle - ctrstate->psxCounters[2].sCycle) >= ctrstate->psxCounters[2].Cycle) { psxRcntReset(ins, 2); } psxRcntSet(ins); }
void psxRcntWtarget(u32 index, u32 value) { // SysPrintf("writeCtarget[%ld] = %lx\n", index, value); psxCounters[index].target = value; psxRcntUpd(index); psxRcntSet(); }
void psxRcntInit(upse_module_instance_t *ins) { upse_psx_counter_state_t *ctrstate; ctrstate = calloc(sizeof(upse_psx_counter_state_t), 1); ctrstate->psxCounters[0].rate = 1; ctrstate->psxCounters[0].interrupt = 0x10; ctrstate->psxCounters[1].rate = 1; ctrstate->psxCounters[1].interrupt = 0x20; ctrstate->psxCounters[2].rate = 1; ctrstate->psxCounters[2].interrupt = 64; ctrstate->psxCounters[3].interrupt = 1; ctrstate->psxCounters[3].mode = 0x58; // The VSync counter mode ctrstate->psxCounters[3].target = 1; ins->ctrstate = ctrstate; psxUpdateVSyncRate(ins); psxRcntUpd(ins, 0); psxRcntUpd(ins, 1); psxRcntUpd(ins, 2); psxRcntUpd(ins, 3); psxRcntSet(ins); ctrstate->last = 0; }
void psxRcntInit(void) { s32 i; // rcnt 0. rcnts[0].rate = 1; rcnts[0].irq = 0x10; // rcnt 1. rcnts[1].rate = 1; rcnts[1].irq = 0x20; // rcnt 2. rcnts[2].rate = 1; rcnts[2].irq = 0x40; // rcnt base. rcnts[3].rate = 1; rcnts[3].mode = RcCountToTarget; psxRcntUVtarget(); rcnts[3].target = rcnt_target; for( i = 0; i < CounterQuantity; ++i ) { _psxRcntWcount( i, 0 ); } psxRcntSet(); }
static void psxRcntReset( u32 index ) { u32 count; if( rcnts[index].counterState == CountToTarget ) { if( rcnts[index].mode & RcCountToTarget ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; count /= rcnts[index].rate; count -= rcnts[index].target; } else { count = _psxRcntRcount( index ); } _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnTarget ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcCountEqTarget; } else if( rcnts[index].counterState == CountToOverflow ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; count /= rcnts[index].rate; count -= 0xffff; _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnOverflow ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { verboseLog( 3, "[RCNT %i] irq: %x\n", index, count ); setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcOverflow; } rcnts[index].mode |= RcUnknown10; psxRcntSet(); }
void psxRcntWtarget(upse_module_instance_t *ins, u32 index, u32 value) { upse_psx_counter_state_t *ctrstate = ins->ctrstate; ctrstate->psxCounters[index].target = value; psxRcntUpd(ins, index); psxRcntSet(ins); }
void psxRcntWcount( u32 index, u32 value ) { verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value ); psxRcntUpdate(); _psxRcntWcount( index, value ); psxRcntSet(); }
void psxRcntWcount( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wcount: %x\n", index, value ); #endif psxRcntUpdate(); _psxRcntWcount( index, value ); psxRcntSet(); }
void psxRcntWtarget( u32 index, u32 value ) { verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value ); psxRcntUpdate(); rcnts[index].target = value; _psxRcntWcount( index, _psxRcntRcount( index ) ); psxRcntSet(); }
void psxRcntWmode( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wmode: %x\n", index, value ); #endif psxRcntUpdate(); rcnts[index].mode = value; rcnts[index].irqState = 0; switch( index ) { case 0: if( value & Rc0PixelClock ) { rcnts[index].rate = 5; } else { rcnts[index].rate = 1; } break; case 1: if( value & Rc1HSyncClock ) { rcnts[index].rate = rcnt_target; } else { rcnts[index].rate = 1; } break; case 2: if( value & Rc2OneEighthClock ) { rcnts[index].rate = 8; } else { rcnts[index].rate = 1; } // TODO: wcount must work. if( value & Rc2Disable ) { rcnts[index].rate = 0xffffffff; } break; } _psxRcntWcount( index, 0 ); psxRcntSet(); }
void psxRcntWmode( u32 index, u32 value ) { verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value ); psxRcntUpdate(); rcnts[index].mode = value; rcnts[index].irqState = 0; switch( index ) { case 0: if( value & Rc0PixelClock ) { rcnts[index].rate = 5; } else { rcnts[index].rate = 1; } break; case 1: if( value & Rc1HSyncClock ) { rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType])); } else { rcnts[index].rate = 1; } break; case 2: if( value & Rc2OneEighthClock ) { rcnts[index].rate = 8; } else { rcnts[index].rate = 1; } // TODO: wcount must work. if( value & Rc2Disable ) { rcnts[index].rate = 0xffffffff; } break; } _psxRcntWcount( index, 0 ); psxRcntSet(); }
void psxRcntWtarget( u32 index, u32 value ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] wtarget: %x\n", index, value ); #endif psxRcntUpdate(); rcnts[index].target = value; _psxRcntWcount( index, _psxRcntRcount( index ) ); psxRcntSet(); }
void psxRcntWmode(upse_module_instance_t *ins, u32 index, u32 value) { upse_psx_counter_state_t *ctrstate = ins->ctrstate; ctrstate->psxCounters[index].mode = value; ctrstate->psxCounters[index].count = 0; if (index == 0) { switch (value & 0x300) { case 0x100: ctrstate->psxCounters[index].rate = ((ctrstate->psxCounters[3].rate /** BIAS*/ ) / 386) / 262; // seems ok break; default: ctrstate->psxCounters[index].rate = 1; } } else if (index == 1) { switch (value & 0x300) { case 0x100: ctrstate->psxCounters[index].rate = (ctrstate->psxCounters[3].rate /** BIAS*/ ) / 262; // seems ok //ctrstate->psxCounters[index].rate = (PSXCLK / 60)/262; //(ctrstate->psxCounters[3].rate*16/262); //printf("%d\n",ctrstate->psxCounters[index].rate); break; default: ctrstate->psxCounters[index].rate = 1; } } else if (index == 2) { switch (value & 0x300) { case 0x200: ctrstate->psxCounters[index].rate = 8; // 1/8 speed break; default: ctrstate->psxCounters[index].rate = 1; // normal speed } } // Need to set a rate and target psxRcntUpd(ins, index); psxRcntSet(ins); }
void psxRcntWmode(u32 index, u32 value) { psxCounters[index].mode = value; psxCounters[index].count = 0; if (index == 0) { switch (value & 0x300) { case 0x100: psxCounters[index].rate = ((psxCounters[3].rate /** BIAS*/ ) / 386) / 262; // seems ok break; default: psxCounters[index].rate = 1; } } else if (index == 1) { switch (value & 0x300) { case 0x100: psxCounters[index].rate = (psxCounters[3].rate /** BIAS*/ ) / 262; // seems ok //psxCounters[index].rate = (PSXCLK / 60)/262; //(psxCounters[3].rate*16/262); //printf("%d\n",psxCounters[index].rate); break; default: psxCounters[index].rate = 1; } } else if (index == 2) { switch (value & 0x300) { case 0x200: psxCounters[index].rate = 8; // 1/8 speed break; default: psxCounters[index].rate = 1; // normal speed } } // Need to set a rate and target psxRcntUpd(index); psxRcntSet(); }
static void psxRcntReset( u32 index ) { u32 count; if( rcnts[index].counterState == CountToTarget ) { if( rcnts[index].mode & RcCountToTarget ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; if (rcnts[index].rate > 1) count = UDIV(count,rcnts[index].rate); count -= rcnts[index].target; } else { count = _psxRcntRcount( index ); } _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnTarget ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] irq: %x\n", index, count ); #endif setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcCountEqTarget; } else if( rcnts[index].counterState == CountToOverflow ) { count = psxRegs.cycle; count -= rcnts[index].cycleStart; if (rcnts[index].rate > 1) count = UDIV(count,rcnts[index].rate); count -= 0xffff; _psxRcntWcount( index, count ); if( rcnts[index].mode & RcIrqOnOverflow ) { if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) ) { #ifdef DEBUG_BIOS dbgf("[RCNT %i] irq: %x\n", index, count ); #endif setIrq( rcnts[index].irq ); rcnts[index].irqState = 1; } } rcnts[index].mode |= RcOverflow; } rcnts[index].mode |= RcUnknown10; psxRcntSet(); }
void psxRcntWcount(u32 index, u32 value) { psxCounters[index].count = value; psxRcntUpd(index); psxRcntSet(); }