static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev) { struct pxaohci_platform_data *inf; uint32_t uhccoms; inf = dev->platform_data; if (cpu_is_pxa3xx()) pxa3xx_u2d_stop_hc(&ohci_to_hcd(&ohci->ohci)->self); if (inf->exit) inf->exit(dev); pxa27x_reset_hc(ohci); /* Host Controller Reset */ uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01; __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS); udelay(10); clk_disable_unprepare(ohci->clk); }
static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) { int retval = 0; struct pxaohci_platform_data *inf; uint32_t uhchr; struct usb_hcd *hcd = dev_get_drvdata(dev); inf = dev_get_platdata(dev); clk_prepare_enable(pxa_ohci->clk); pxa27x_reset_hc(pxa_ohci); uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR; __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR) cpu_relax(); pxa27x_setup_hc(pxa_ohci, inf); if (inf->init) retval = inf->init(dev); if (retval < 0) return retval; if (cpu_is_pxa3xx()) pxa3xx_u2d_start_hc(&hcd->self); uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE; __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE); /* Clear any OTG Pin Hold */ pxa27x_clear_otgph(); return 0; }
static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev) { struct pxaohci_platform_data *inf; struct usb_hcd *hcd = dev_get_drvdata(dev); uint32_t uhccoms; inf = dev_get_platdata(dev); if (cpu_is_pxa3xx()) pxa3xx_u2d_stop_hc(&hcd->self); if (inf->exit) inf->exit(dev); pxa27x_reset_hc(pxa_ohci); /* Host Controller Reset */ uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01; __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); udelay(10); clk_disable_unprepare(pxa_ohci->clk); }