static void digic_init(Object *obj) { DigicState *s = DIGIC(obj); DeviceState *dev; int i; object_initialize(&s->cpu, sizeof(s->cpu), "arm946-" TYPE_ARM_CPU); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { #define DIGIC_TIMER_NAME_MLEN 11 char name[DIGIC_TIMER_NAME_MLEN]; object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_DIGIC_TIMER); dev = DEVICE(&s->timer[i]); qdev_set_parent_bus(dev, sysbus_get_default()); snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i); object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL); } object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART); dev = DEVICE(&s->uart); qdev_set_parent_bus(dev, sysbus_get_default()); object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL); }
static void virtio_gpu_pci_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOGPUPCIBase *vgpu = VIRTIO_GPU_PCI_BASE(vpci_dev); VirtIOGPUBase *g = vgpu->vgpu; DeviceState *vdev = DEVICE(g); int i; Error *local_error = NULL; qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); if (!virtio_pci_force_virtio_1(vpci_dev, errp)) { return; } object_property_set_bool(OBJECT(vdev), true, "realized", &local_error); if (local_error) { error_propagate(errp, local_error); return; } for (i = 0; i < g->conf.max_outputs; i++) { object_property_set_link(OBJECT(g->scanout[i].con), OBJECT(vpci_dev), "device", errp); } }
static int q35_host_init(SysBusDevice *dev) { PCIBus *b; PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev); Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev); memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci, "pci-conf-idx", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci, "pci-conf-data", 4); sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); if (pcie_host_init(&s->host) < 0) { return -1; } b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); s->host.pci.bus = b; qdev_set_parent_bus(DEVICE(&s->mch), BUS(b)); qdev_init_nofail(DEVICE(&s->mch)); return 0; }
void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); }
static void virtio_serial_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOSerialPCI *dev = VIRTIO_SERIAL_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); DeviceState *proxy = DEVICE(vpci_dev); char *bus_name; if (vpci_dev->class_code != PCI_CLASS_COMMUNICATION_OTHER && vpci_dev->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */ vpci_dev->class_code != PCI_CLASS_OTHERS) { /* qemu-kvm */ vpci_dev->class_code = PCI_CLASS_COMMUNICATION_OTHER; } /* backwards-compatibility with machines that were created with DEV_NVECTORS_UNSPECIFIED */ if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) { vpci_dev->nvectors = dev->vdev.serial.max_virtserial_ports + 1; } /* * For command line compatibility, this sets the virtio-serial-device bus * name as before. */ if (proxy->id) { bus_name = g_strdup_printf("%s.0", proxy->id); virtio_device_set_child_bus_name(VIRTIO_DEVICE(vdev), bus_name); g_free(bus_name); } qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); object_property_set_bool(OBJECT(vdev), true, "realized", errp); }
/* VGA device wrapper around PCI device around virtio GPU */ static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOVGA *vvga = VIRTIO_VGA(vpci_dev); VirtIOGPU *g = &vvga->vdev; VGACommonState *vga = &vvga->vga; Error *err = NULL; uint32_t offset; int i; /* init vga compat bits */ vga->vram_size_mb = 8; vga_common_init(vga, OBJECT(vpci_dev), false); vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev), pci_address_space_io(&vpci_dev->pci_dev), true); pci_register_bar(&vpci_dev->pci_dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); /* * Configure virtio bar and regions * * We use bar #2 for the mmio regions, to be compatible with stdvga. * virtio regions are moved to the end of bar #2, to make room for * the stdvga mmio registers at the start of bar #2. */ vpci_dev->modern_mem_bar = 2; vpci_dev->msix_bar = 4; offset = memory_region_size(&vpci_dev->modern_bar); offset -= vpci_dev->notify.size; vpci_dev->notify.offset = offset; offset -= vpci_dev->device.size; vpci_dev->device.offset = offset; offset -= vpci_dev->isr.size; vpci_dev->isr.offset = offset; offset -= vpci_dev->common.size; vpci_dev->common.offset = offset; /* init virtio bits */ qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus)); /* force virtio-1.0 */ vpci_dev->flags &= ~VIRTIO_PCI_FLAG_DISABLE_MODERN; vpci_dev->flags |= VIRTIO_PCI_FLAG_DISABLE_LEGACY; object_property_set_bool(OBJECT(g), true, "realized", &err); if (err) { error_propagate(errp, err); return; } /* add stdvga mmio regions */ pci_std_vga_mmio_region_init(vga, &vpci_dev->modern_bar, vvga->vga_mrs, true); vga->con = g->scanout[0].con; graphic_console_set_hwops(vga->con, &virtio_vga_ops, vvga); for (i = 0; i < g->conf.max_outputs; i++) { object_property_set_link(OBJECT(g->scanout[i].con), OBJECT(vpci_dev), "device", errp); } }
static void xilinx_pcie_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci = PCI_HOST_BRIDGE(dev); XilinxPCIEHost *s = XILINX_PCIE_HOST(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); snprintf(s->name, sizeof(s->name), "pcie%u", s->bus_nr); /* PCI configuration space */ pcie_host_mmcfg_init(pex, s->cfg_size); /* MMIO region */ memory_region_init(&s->mmio, OBJECT(s), "mmio", UINT64_MAX); memory_region_set_enabled(&s->mmio, false); /* dummy PCI I/O region (not visible to the CPU) */ memory_region_init(&s->io, OBJECT(s), "io", 16); /* interrupt out */ qdev_init_gpio_out_named(dev, &s->irq, "interrupt_out", 1); sysbus_init_mmio(sbd, &pex->mmio); sysbus_init_mmio(sbd, &s->mmio); pci->bus = pci_register_root_bus(dev, s->name, xilinx_pcie_set_irq, pci_swizzle_map_irq_fn, s, &s->mmio, &s->io, 0, 4, TYPE_PCIE_BUS); qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus)); qdev_init_nofail(DEVICE(&s->root)); }
static void macio_instance_init(Object *obj) { MacIOState *s = MACIO(obj); memory_region_init(&s->bar, obj, "macio", 0x80000); object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA); qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default()); object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL); object_initialize(&s->escc, sizeof(s->escc), TYPE_ESCC); qdev_set_parent_bus(DEVICE(&s->escc), sysbus_get_default()); object_property_add_child(obj, "escc", OBJECT(&s->escc), NULL); }
static void bcm2836_init(Object *obj) { BCM2836State *s = BCM2836(obj); object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); qdev_set_parent_bus(DEVICE(&s->control), sysbus_get_default()); object_initialize(&s->peripherals, sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals), &error_abort); object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), "board-rev", &error_abort); object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), "vcram-size", &error_abort); qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default()); }
static void init_sysbus_child(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize(child, childsize, childtype); object_property_add_child(parent, childname, OBJECT(child), &error_abort); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); }
static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio = opaque; object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); }
static void stm32f205_soc_initfn(Object *obj) { STM32F205State *s = STM32F205_SOC(obj); int i; object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); for (i = 0; i < STM_NUM_USARTS; i++) { object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F2XX_USART); qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); } for (i = 0; i < STM_NUM_TIMERS; i++) { object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); } }
DeviceState *aux_create_slave(AUXBus *bus, const char *type, uint32_t addr) { DeviceState *dev; dev = DEVICE(object_new(type)); assert(dev); qdev_set_parent_bus(dev, &bus->qbus); qdev_init_nofail(dev); aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev), addr); return dev; }
static int virtio_ccw_scsi_init(VirtioCcwDevice *ccw_dev) { VirtIOSCSICcw *dev = VIRTIO_SCSI_CCW(ccw_dev); DeviceState *vdev = DEVICE(&dev->vdev); qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus)); if (qdev_init(vdev) < 0) { return -1; } return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev)); }
static void xlnx_zynqmp_pmu_init(MachineState *machine) { XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *pmu_rom = g_new(MemoryRegion, 1); MemoryRegion *pmu_ram = g_new(MemoryRegion, 1); XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS]; qemu_irq irq[32]; int i; /* Create the ROM */ memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom", XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR, pmu_rom); /* Create the RAM */ memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR, pmu_ram); /* Create the PMU device */ object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC); object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu), &error_abort); object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal); for (i = 0; i < 32; i++) { irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i); } /* Create and connect the IPI device */ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { ipi[i] = g_new0(XlnxZynqMPIPI, 1); object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI); qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default()); } for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { object_property_set_bool(OBJECT(ipi[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]); } /* Load the kernel */ microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, machine->ram_size, machine->initrd_filename, machine->dtb, NULL); }
static int virtio_ccw_blk_init(VirtioCcwDevice *ccw_dev) { VirtIOBlkCcw *dev = VIRTIO_BLK_CCW(ccw_dev); DeviceState *vdev = DEVICE(&dev->vdev); virtio_blk_set_conf(vdev, &(dev->blk)); qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus)); if (qdev_init(vdev) < 0) { return -1; } return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev)); }
static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size, int index) { gchar *name; object_initialize(ide, ide_size, TYPE_MACIO_IDE); qdev_set_parent_bus(DEVICE(ide), sysbus_get_default()); memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000), &ide->mem); name = g_strdup_printf("ide[%i]", index); object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL); g_free(name); }
static void a9mp_priv_initfn(Object *obj) { A9MPPrivState *s = A9MPCORE_PRIV(obj); memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); }
static void vhost_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VHostSCSIPCI *dev = VHOST_SCSI_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); VirtIOSCSICommon *vs = VIRTIO_SCSI_COMMON(vdev); if (vpci_dev->nvectors == DEV_NVECTORS_UNSPECIFIED) { vpci_dev->nvectors = vs->conf.num_queues + 3; } qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); object_property_set_bool(OBJECT(vdev), true, "realized", errp); }
static void mpcore_priv_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); memory_region_init(&s->container, OBJECT(s), "mpcore-priv-container", 0x2000); sysbus_init_mmio(sbd, &s->container); object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); /* Request the legacy 11MPCore GIC behaviour: */ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); }
static void macio_instance_init(Object *obj) { MacIOState *s = MACIO(obj); MemoryRegion *dbdma_mem; memory_region_init(&s->bar, NULL, "macio", 0x80000); object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); s->dbdma = DBDMA_init(&dbdma_mem); memory_region_add_subregion(&s->bar, 0x08000, dbdma_mem); }
static void bcm2835_init(Object *obj) { BCM2835State *s = BCM2835(obj); object_initialize(&s->cpu, sizeof(s->cpu), "arm1176-" TYPE_ARM_CPU); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), &error_abort); object_initialize(&s->peripherals, sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals), &error_abort); object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), "vcram-size", &error_abort); qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default()); }
static int virtio_ccw_net_init(VirtioCcwDevice *ccw_dev) { DeviceState *qdev = DEVICE(ccw_dev); VirtIONetCcw *dev = VIRTIO_NET_CCW(ccw_dev); DeviceState *vdev = DEVICE(&dev->vdev); virtio_net_set_config_size(&dev->vdev, ccw_dev->host_features[0]); virtio_net_set_netclient_name(&dev->vdev, qdev->id, object_get_typename(OBJECT(qdev))); qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus)); if (qdev_init(vdev) < 0) { return -1; } return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev)); }
static int virtio_ccw_rng_init(VirtioCcwDevice *ccw_dev) { VirtIORNGCcw *dev = VIRTIO_RNG_CCW(ccw_dev); DeviceState *vdev = DEVICE(&dev->vdev); qdev_set_parent_bus(vdev, BUS(&ccw_dev->bus)); if (qdev_init(vdev) < 0) { return -1; } object_property_set_link(OBJECT(dev), OBJECT(dev->vdev.conf.rng), "rng", NULL); return virtio_ccw_device_init(ccw_dev, VIRTIO_DEVICE(vdev)); }
static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2SCC *scc = opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); sccdev = DEVICE(scc); qdev_set_parent_bus(sccdev, sysbus_get_default()); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); }
static void virtio_gpu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VirtIOGPUPCI *vgpu = VIRTIO_GPU_PCI(vpci_dev); VirtIOGPU *g = &vgpu->vdev; DeviceState *vdev = DEVICE(&vgpu->vdev); int i; qdev_set_parent_bus(vdev, BUS(&vpci_dev->bus)); virtio_pci_force_virtio_1(vpci_dev); object_property_set_bool(OBJECT(vdev), true, "realized", errp); for (i = 0; i < g->conf.max_outputs; i++) { object_property_set_link(OBJECT(g->scanout[i].con), OBJECT(vpci_dev), "device", errp); } }
static void macio_oldworld_init(Object *obj) { MacIOState *s = MACIO(obj); OldWorldMacIOState *os = OLDWORLD_MACIO(obj); DeviceState *dev; qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs)); object_initialize(&os->nvram, TYPE_MACIO_NVRAM); dev = DEVICE(&os->nvram); qdev_prop_set_uint32(dev, "size", 0x2000); qdev_prop_set_uint32(dev, "it_shift", 4); object_initialize(&os->ide, TYPE_MACIO_IDE); qdev_set_parent_bus(DEVICE(&os->ide), sysbus_get_default()); memory_region_add_subregion(&s->bar, 0x1f000 + (1 * 0x1000), &os->ide.mem); object_property_add_child(obj, "ide", OBJECT(&os->ide), NULL); }
static void q35_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci = PCI_HOST_BRIDGE(dev); Q35PCIHost *s = Q35_HOST_DEVICE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); pci->bus = pci_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); qdev_init_nofail(DEVICE(&s->mch)); }
static void fsl_imx25_init(Object *obj) { FslIMX25State *s = FSL_IMX25(obj); int i; object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM); qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT); qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); } object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC); qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default()); for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); } }
static void raven_pcihost_initfn(Object *obj) { PCIHostState *h = PCI_HOST_BRIDGE(obj); PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *address_space_io = get_system_io(); DeviceState *pci_dev; pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), NULL, address_space_mem, address_space_io, 0); h->bus = &s->pci_bus; object_initialize(&s->pci_dev, TYPE_RAVEN_PCI_DEVICE); pci_dev = DEVICE(&s->pci_dev); qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus)); object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr", NULL); qdev_prop_set_bit(pci_dev, "multifunction", false); }