static int tcx_load(QEMUFile *f, void *opaque, int version_id) { TCXState *s = opaque; uint32_t dummy; if (version_id != 3 && version_id != 4) return -EINVAL; if (version_id == 3) { qemu_get_be32s(f, &dummy); qemu_get_be32s(f, &dummy); qemu_get_be32s(f, &dummy); } qemu_get_be16s(f, &s->height); qemu_get_be16s(f, &s->width); qemu_get_be16s(f, &s->depth); qemu_get_buffer(f, s->r, 256); qemu_get_buffer(f, s->g, 256); qemu_get_buffer(f, s->b, 256); qemu_get_8s(f, &s->dac_index); qemu_get_8s(f, &s->dac_state); update_palette_entries(s, 0, 256); if (s->depth == 24) tcx24_invalidate_display(s); else tcx_invalidate_display(s); return 0; }
static void ps2_common_load (QEMUFile *f, PS2State *s) { qemu_get_be32s (f, &s->write_cmd); qemu_get_be32s (f, &s->queue.rptr); qemu_get_be32s (f, &s->queue.wptr); qemu_get_be32s (f, &s->queue.count); qemu_get_buffer (f, s->queue.data, sizeof (s->queue.data)); }
static int get_cpudouble(QEMUFile *f, void *pv, size_t size, VMStateField *field) { CPU_DoubleU *v = pv; qemu_get_be32s(f, &v->l.upper); qemu_get_be32s(f, &v->l.lower); return 0; }
void cpu_get_timer(QEMUFile *f, CPUTimer *s) { qemu_get_be32s(f, &s->frequency); qemu_get_be32s(f, &s->disabled); qemu_get_be64s(f, &s->disabled_mask); qemu_get_sbe64s(f, &s->clock_offset); qemu_get_timer(f, s->qtimer); }
static int ps2_kbd_load(QEMUFile* f, void* opaque, int version_id) { PS2KbdState *s = (PS2KbdState*)opaque; if (version_id != 2) return -EINVAL; ps2_common_load (f, &s->common); qemu_get_be32s(f, &s->scan_enabled); qemu_get_be32s(f, &s->translate); return 0; }
static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu) { int i; for(i = 0; i < 32; i++) qemu_get_be64s(f, &fpu->fpr[i].d); qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess); qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode); qemu_get_s8s(f, &fpu->fp_status.float_exception_flags); qemu_get_be32s(f, &fpu->fcr0); qemu_get_be32s(f, &fpu->fcr31); }
static int get_tlb(QEMUFile *f, void *pv, size_t size) { r4k_tlb_t *v = pv; uint16_t flags; qemu_get_betls(f, &v->VPN); qemu_get_be32s(f, &v->PageMask); qemu_get_8s(f, &v->ASID); qemu_get_be16s(f, &flags); v->G = (flags >> 10) & 1; v->C0 = (flags >> 7) & 3; v->C1 = (flags >> 4) & 3; v->V0 = (flags >> 3) & 1; v->V1 = (flags >> 2) & 1; v->D0 = (flags >> 1) & 1; v->D1 = (flags >> 0) & 1; v->EHINV = (flags >> 15) & 1; v->RI1 = (flags >> 14) & 1; v->RI0 = (flags >> 13) & 1; v->XI1 = (flags >> 12) & 1; v->XI0 = (flags >> 11) & 1; qemu_get_betls(f, &v->PFN[0]); qemu_get_betls(f, &v->PFN[1]); return 0; }
static int pxa2xx_keypad_load(QEMUFile *f, void *opaque, int version_id) { PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque; qemu_get_be32s(f, &s->kpc); qemu_get_be32s(f, &s->kpdk); qemu_get_be32s(f, &s->kprec); qemu_get_be32s(f, &s->kpmk); qemu_get_be32s(f, &s->kpas); qemu_get_be32s(f, &s->kpasmkp[0]); qemu_get_be32s(f, &s->kpasmkp[1]); qemu_get_be32s(f, &s->kpasmkp[2]); qemu_get_be32s(f, &s->kpasmkp[3]); qemu_get_be32s(f, &s->kpkdi); return 0; }
static int get_uint32_equal(QEMUFile *f, void *pv, size_t size) { uint32_t *v = pv; uint32_t v2; qemu_get_be32s(f, &v2); if (*v == v2) { return 0; } return -EINVAL; }
static int ps2_mouse_load(QEMUFile* f, void* opaque, int version_id) { PS2MouseState *s = (PS2MouseState*)opaque; if (version_id != 2) return -EINVAL; ps2_common_load (f, &s->common); qemu_get_8s(f, &s->mouse_status); qemu_get_8s(f, &s->mouse_resolution); qemu_get_8s(f, &s->mouse_sample_rate); qemu_get_8s(f, &s->mouse_wrap); qemu_get_8s(f, &s->mouse_type); qemu_get_8s(f, &s->mouse_detect_state); qemu_get_be32s(f, &s->mouse_dx); qemu_get_be32s(f, &s->mouse_dy); qemu_get_be32s(f, &s->mouse_dz); qemu_get_8s(f, &s->mouse_buttons); return 0; }
static int dma_load(QEMUFile *f, void *opaque, int version_id) { DMAState *s = opaque; unsigned int i; if (version_id != 1) return -EINVAL; for (i = 0; i < DMA_REGS; i++) qemu_get_be32s(f, &s->dmaregs[i]); return 0; }
static int get_uint32_equal(QEMUFile *f, void *pv, size_t size, VMStateField *field) { uint32_t *v = pv; uint32_t v2; qemu_get_be32s(f, &v2); if (*v == v2) { return 0; } error_report("%" PRIx32 " != %" PRIx32, *v, v2); return -EINVAL; }
static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) { PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque; int i; qemu_get_be32s(f, &s->status); qemu_get_be32s(f, &s->clkrt); qemu_get_be32s(f, &s->spi); qemu_get_be32s(f, &s->cmdat); qemu_get_be32s(f, &s->resp_tout); qemu_get_be32s(f, &s->read_tout); s->blklen = qemu_get_be32(f); s->numblk = qemu_get_be32(f); qemu_get_be32s(f, &s->intmask); qemu_get_be32s(f, &s->intreq); s->cmd = qemu_get_be32(f); qemu_get_be32s(f, &s->arg); s->cmdreq = qemu_get_be32(f); s->active = qemu_get_be32(f); s->bytesleft = qemu_get_be32(f); s->tx_len = qemu_get_byte(f); s->tx_start = 0; if (s->tx_len >= sizeof(s->tx_fifo) || s->tx_len < 0) return -EINVAL; for (i = 0; i < s->tx_len; i ++) s->tx_fifo[i] = qemu_get_byte(f); s->rx_len = qemu_get_byte(f); s->rx_start = 0; if (s->rx_len >= sizeof(s->rx_fifo) || s->rx_len < 0) return -EINVAL; for (i = 0; i < s->rx_len; i ++) s->rx_fifo[i] = qemu_get_byte(f); s->resp_len = qemu_get_byte(f); if (s->resp_len > 9 || s->resp_len < 0) return -EINVAL; for (i = s->resp_len; i < 9; i ++) qemu_get_be16s(f, &s->resp_fifo[i]); return 0; }
static int cs_load(QEMUFile *f, void *opaque, int version_id) { CSState *s = opaque; unsigned int i; if (version_id > 1) return -EINVAL; for (i = 0; i < CS_REGS; i++) qemu_get_be32s(f, &s->regs[i]); qemu_get_buffer(f, s->dregs, CS_DREGS); return 0; }
static int sbi_load(QEMUFile *f, void *opaque, int version_id) { SBIState *s = opaque; unsigned int i; if (version_id != 1) return -EINVAL; for (i = 0; i < MAX_CPUS; i++) { qemu_get_be32s(f, &s->intreg_pending[i]); } return 0; }
int virtio_load(VirtIODevice *vdev, QEMUFile *f) { int num, i, ret; uint32_t features; uint32_t supported_features = vdev->binding->get_features(vdev->binding_opaque); if (vdev->binding->load_config) { ret = vdev->binding->load_config(vdev->binding_opaque, f); if (ret) return ret; } qemu_get_8s(f, &vdev->status); qemu_get_8s(f, &vdev->isr); qemu_get_be16s(f, &vdev->queue_sel); qemu_get_be32s(f, &features); if (features & ~supported_features) { fprintf(stderr, "Features 0x%x unsupported. Allowed features: 0x%x\n", features, supported_features); return -1; } vdev->guest_features = features; vdev->config_len = qemu_get_be32(f); qemu_get_buffer(f, vdev->config, vdev->config_len); num = qemu_get_be32(f); for (i = 0; i < num; i++) { vdev->vq[i].vring.num = qemu_get_be32(f); vdev->vq[i].pa = qemu_get_be64(f); qemu_get_be16s(f, &vdev->vq[i].last_avail_idx); if (vdev->vq[i].pa) { virtqueue_init(&vdev->vq[i]); } if (vdev->binding->load_queue) { ret = vdev->binding->load_queue(vdev->binding_opaque, i, f); if (ret) return ret; } } virtio_notify_vector(vdev, VIRTIO_NO_VECTOR); return 0; }
static int vmmouse_load(QEMUFile *f, void *opaque, int version_id) { VMMouseState *s = (VMMouseState *)opaque; int i; if (version_id != 0) return -EINVAL; if (qemu_get_be32(f) != VMMOUSE_QUEUE_SIZE) return -EINVAL; for (i = 0; i < VMMOUSE_QUEUE_SIZE; i++) qemu_get_be32s(f, &s->queue[i]); qemu_get_be16s(f, &s->nb_queue); qemu_get_be16s(f, &s->status); qemu_get_8s(f, &s->absolute); vmmouse_update_handler(s); return 0; }
static int s3c_rtc_load(QEMUFile *f, void *opaque, int version_id) { struct s3c_rtc_state_s *s = (struct s3c_rtc_state_s *) opaque; qemu_get_sbe64s(f, &s->next); qemu_get_8s(f, &s->control); qemu_get_8s(f, &s->tick); qemu_get_8s(f, &s->alarm); qemu_get_8s(f, &s->almsec); qemu_get_8s(f, &s->almmin); qemu_get_8s(f, &s->almday); qemu_get_8s(f, &s->almhour); qemu_get_8s(f, &s->almmon); qemu_get_8s(f, &s->almyear); qemu_get_8s(f, &s->reset); qemu_get_be32s(f, &s->sec); s->enable = (s->control == 0x1); s3c_rtc_tick_mod(s); return 0; }
static int mipsnet_load(QEMUFile *f, void *opaque, int version_id) { MIPSnetState *s = opaque; if (version_id > 0) return -EINVAL; qemu_get_be32s(f, &s->busy); qemu_get_be32s(f, &s->rx_count); qemu_get_be32s(f, &s->rx_read); qemu_get_be32s(f, &s->tx_count); qemu_get_be32s(f, &s->tx_written); qemu_get_be32s(f, &s->intctl); qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE); qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE); return 0; }
static int esp_load(QEMUFile *f, void *opaque, int version_id) { ESPState *s = opaque; if (version_id != 3) return -EINVAL; // Cannot emulate 2 qemu_get_buffer(f, s->rregs, ESP_REGS); qemu_get_buffer(f, s->wregs, ESP_REGS); qemu_get_sbe32s(f, &s->ti_size); qemu_get_be32s(f, &s->ti_rptr); qemu_get_be32s(f, &s->ti_wptr); qemu_get_buffer(f, s->ti_buf, TI_BUFSZ); qemu_get_be32s(f, &s->sense); qemu_get_be32s(f, &s->dma); qemu_get_buffer(f, s->cmdbuf, TI_BUFSZ); qemu_get_be32s(f, &s->cmdlen); qemu_get_be32s(f, &s->do_cmd); qemu_get_be32s(f, &s->dma_left); return 0; }
static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id) { if (version_id > 2) return -EINVAL; qemu_get_be32s(f, &s->irq); qemu_get_be32s(f, &s->reg); qemu_get_be32s(f, &s->rxint); qemu_get_be32s(f, &s->txint); if (version_id >= 2) { qemu_get_be32s(f, &s->rxint_under_svc); qemu_get_be32s(f, &s->txint_under_svc); } qemu_get_8s(f, &s->rx); qemu_get_8s(f, &s->tx); qemu_get_buffer(f, s->wregs, 16); qemu_get_buffer(f, s->rregs, 16); return 0; }
static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id) { int tmp; if (version_id > 2) return -EINVAL; qemu_get_be32s(f, &tmp); /* unused */ qemu_get_be32s(f, &s->reg); qemu_get_be32s(f, &s->rxint); qemu_get_be32s(f, &s->txint); if (version_id >= 2) { qemu_get_be32s(f, &s->rxint_under_svc); qemu_get_be32s(f, &s->txint_under_svc); } qemu_get_8s(f, &s->rx); qemu_get_8s(f, &s->tx); qemu_get_buffer(f, s->wregs, SERIAL_REGS); qemu_get_buffer(f, s->rregs, SERIAL_REGS); return 0; }
int generic_usb_load(QEMUFile* f, void *opaque, int version_id) { USBDevice *s = (USBDevice*)opaque; if (version_id != 1) return -EINVAL; qemu_get_be32s(f, &s->speed); qemu_get_8s(f, &s->addr); qemu_get_be32s(f, &s->state); qemu_get_buffer(f, s->setup_buf, 8); qemu_get_buffer(f, s->data_buf, 1024); qemu_get_be32s(f, &s->remote_wakeup); qemu_get_be32s(f, &s->setup_state); qemu_get_be32s(f, &s->setup_len); qemu_get_be32s(f, &s->setup_index); return 0; }
static int ppc4xx_pci_load(QEMUFile *f, void *opaque, int version_id) { PPC4xxPCIState *controller = opaque; int i; if (version_id != 1) return -EINVAL; pci_device_load(controller->pci_dev, f); for (i = 0; i < PPC4xx_PCI_NR_PMMS; i++) { qemu_get_be32s(f, &controller->pmm[i].la); qemu_get_be32s(f, &controller->pmm[i].ma); qemu_get_be32s(f, &controller->pmm[i].pcila); qemu_get_be32s(f, &controller->pmm[i].pciha); } for (i = 0; i < PPC4xx_PCI_NR_PTMS; i++) { qemu_get_be32s(f, &controller->ptm[i].ms); qemu_get_be32s(f, &controller->ptm[i].la); } return 0; }
int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUMIPSState *env = opaque; int i; if (version_id != 3) return -EINVAL; /* Load active TC */ load_tc(f, &env->active_tc); /* Load active FPU */ load_fpu(f, &env->active_fpu); /* Load MVP */ qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl); qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0); qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1); /* Load TLB */ qemu_get_be32s(f, &env->tlb->nb_tlb); for(i = 0; i < MIPS_TLB_MAX; i++) { uint16_t flags; uint8_t asid; qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN); qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask); qemu_get_8s(f, &asid); env->tlb->mmu.r4k.tlb[i].ASID = asid; qemu_get_be16s(f, &flags); env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1; env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3; env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3; env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1; env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1; env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1; env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1; qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]); qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]); } /* Load CPU metastate */ qemu_get_be32s(f, &env->current_tc); qemu_get_be32s(f, &env->current_fpu); qemu_get_sbe32s(f, &env->error_code); qemu_get_be32s(f, &env->hflags); qemu_get_betls(f, &env->btarget); qemu_get_sbe32s(f, &i); env->bcond = i; /* Load remaining CP1 registers */ qemu_get_sbe32s(f, &env->CP0_Index); qemu_get_sbe32s(f, &env->CP0_Random); qemu_get_sbe32s(f, &env->CP0_VPEControl); qemu_get_sbe32s(f, &env->CP0_VPEConf0); qemu_get_sbe32s(f, &env->CP0_VPEConf1); qemu_get_betls(f, &env->CP0_YQMask); qemu_get_betls(f, &env->CP0_VPESchedule); qemu_get_betls(f, &env->CP0_VPEScheFBack); qemu_get_sbe32s(f, &env->CP0_VPEOpt); qemu_get_betls(f, &env->CP0_EntryLo0); qemu_get_betls(f, &env->CP0_EntryLo1); qemu_get_betls(f, &env->CP0_Context); qemu_get_sbe32s(f, &env->CP0_PageMask); qemu_get_sbe32s(f, &env->CP0_PageGrain); qemu_get_sbe32s(f, &env->CP0_Wired); qemu_get_sbe32s(f, &env->CP0_SRSConf0); qemu_get_sbe32s(f, &env->CP0_SRSConf1); qemu_get_sbe32s(f, &env->CP0_SRSConf2); qemu_get_sbe32s(f, &env->CP0_SRSConf3); qemu_get_sbe32s(f, &env->CP0_SRSConf4); qemu_get_sbe32s(f, &env->CP0_HWREna); qemu_get_betls(f, &env->CP0_BadVAddr); qemu_get_sbe32s(f, &env->CP0_Count); qemu_get_betls(f, &env->CP0_EntryHi); qemu_get_sbe32s(f, &env->CP0_Compare); qemu_get_sbe32s(f, &env->CP0_Status); qemu_get_sbe32s(f, &env->CP0_IntCtl); qemu_get_sbe32s(f, &env->CP0_SRSCtl); qemu_get_sbe32s(f, &env->CP0_SRSMap); qemu_get_sbe32s(f, &env->CP0_Cause); qemu_get_betls(f, &env->CP0_EPC); qemu_get_sbe32s(f, &env->CP0_PRid); qemu_get_sbe32s(f, &env->CP0_EBase); qemu_get_sbe32s(f, &env->CP0_Config0); qemu_get_sbe32s(f, &env->CP0_Config1); qemu_get_sbe32s(f, &env->CP0_Config2); qemu_get_sbe32s(f, &env->CP0_Config3); qemu_get_sbe32s(f, &env->CP0_Config6); qemu_get_sbe32s(f, &env->CP0_Config7); qemu_get_betls(f, &env->lladdr); for(i = 0; i < 8; i++) qemu_get_betls(f, &env->CP0_WatchLo[i]); for(i = 0; i < 8; i++) qemu_get_sbe32s(f, &env->CP0_WatchHi[i]); qemu_get_betls(f, &env->CP0_XContext); qemu_get_sbe32s(f, &env->CP0_Framemask); qemu_get_sbe32s(f, &env->CP0_Debug); qemu_get_betls(f, &env->CP0_DEPC); qemu_get_sbe32s(f, &env->CP0_Performance0); qemu_get_sbe32s(f, &env->CP0_TagLo); qemu_get_sbe32s(f, &env->CP0_DataLo); qemu_get_sbe32s(f, &env->CP0_TagHi); qemu_get_sbe32s(f, &env->CP0_DataHi); qemu_get_betls(f, &env->CP0_ErrorEPC); qemu_get_sbe32s(f, &env->CP0_DESAVE); /* Load inactive TC state */ for (i = 0; i < MIPS_SHADOW_SET_MAX; i++) load_tc(f, &env->tcs[i]); for (i = 0; i < MIPS_FPU_MAX; i++) load_fpu(f, &env->fpus[i]); /* XXX: ensure compatiblity for halted bit ? */ tlb_flush(env, 1); return 0; }
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) { PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; unsigned int i, j; target_ulong sdr1; uint32_t fpscr; target_ulong xer; for (i = 0; i < 32; i++) qemu_get_betls(f, &env->gpr[i]); #if !defined(TARGET_PPC64) for (i = 0; i < 32; i++) qemu_get_betls(f, &env->gprh[i]); #endif qemu_get_betls(f, &env->lr); qemu_get_betls(f, &env->ctr); for (i = 0; i < 8; i++) qemu_get_be32s(f, &env->crf[i]); qemu_get_betls(f, &xer); cpu_write_xer(env, xer); qemu_get_betls(f, &env->reserve_addr); qemu_get_betls(f, &env->msr); for (i = 0; i < 4; i++) qemu_get_betls(f, &env->tgpr[i]); for (i = 0; i < 32; i++) { union { float64 d; uint64_t l; } u; u.l = qemu_get_be64(f); env->fpr[i] = u.d; } qemu_get_be32s(f, &fpscr); env->fpscr = fpscr; qemu_get_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) qemu_get_betls(f, &env->spr[SPR_ASR]); qemu_get_sbe32s(f, &env->slb_nr); #endif qemu_get_betls(f, &sdr1); for (i = 0; i < 32; i++) qemu_get_betls(f, &env->sr[i]); for (i = 0; i < 2; i++) for (j = 0; j < 8; j++) qemu_get_betls(f, &env->DBAT[i][j]); for (i = 0; i < 2; i++) for (j = 0; j < 8; j++) qemu_get_betls(f, &env->IBAT[i][j]); qemu_get_sbe32s(f, &env->nb_tlb); qemu_get_sbe32s(f, &env->tlb_per_way); qemu_get_sbe32s(f, &env->nb_ways); qemu_get_sbe32s(f, &env->last_way); qemu_get_sbe32s(f, &env->id_tlbs); qemu_get_sbe32s(f, &env->nb_pids); if (env->tlb.tlb6) { // XXX assumes 6xx for (i = 0; i < env->nb_tlb; i++) { qemu_get_betls(f, &env->tlb.tlb6[i].pte0); qemu_get_betls(f, &env->tlb.tlb6[i].pte1); qemu_get_betls(f, &env->tlb.tlb6[i].EPN); } } for (i = 0; i < 4; i++) qemu_get_betls(f, &env->pb[i]); for (i = 0; i < 1024; i++) qemu_get_betls(f, &env->spr[i]); if (!env->external_htab) { ppc_store_sdr1(env, sdr1); } qemu_get_be32s(f, &env->vscr); qemu_get_be64s(f, &env->spe_acc); qemu_get_be32s(f, &env->spe_fscr); qemu_get_betls(f, &env->msr_mask); qemu_get_be32s(f, &env->flags); qemu_get_sbe32s(f, &env->error_code); qemu_get_be32s(f, &env->pending_interrupts); qemu_get_be32s(f, &env->irq_input_state); for (i = 0; i < POWERPC_EXCP_NB; i++) qemu_get_betls(f, &env->excp_vectors[i]); qemu_get_betls(f, &env->excp_prefix); qemu_get_betls(f, &env->ivor_mask); qemu_get_betls(f, &env->ivpr_mask); qemu_get_betls(f, &env->hreset_vector); qemu_get_betls(f, &env->nip); qemu_get_betls(f, &env->hflags); qemu_get_betls(f, &env->hflags_nmsr); qemu_get_sbe32s(f, &env->mmu_idx); qemu_get_sbe32(f); /* Discard unused power_mode */ return 0; }
static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id) { pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque; int64_t now; int i; qemu_get_be32s(f, &s->clock); qemu_get_be32s(f, &s->oldclock); qemu_get_be64s(f, &s->lastload); now = qemu_get_clock(vm_clock); for (i = 0; i < 4; i ++) { qemu_get_be32s(f, &s->timer[i].value); s->timer[i].level = qemu_get_be32(f); } pxa2xx_timer_update(s, now); if (s->tm4) for (i = 0; i < 8; i ++) { qemu_get_be32s(f, &s->tm4[i].tm.value); s->tm4[i].tm.level = qemu_get_be32(f); qemu_get_be32s(f, &s->tm4[i].oldclock); qemu_get_be32s(f, &s->tm4[i].clock); qemu_get_be64s(f, &s->tm4[i].lastload); qemu_get_be32s(f, &s->tm4[i].freq); qemu_get_be32s(f, &s->tm4[i].control); pxa2xx_timer_update4(s, now, i); } qemu_get_be32s(f, &s->events); qemu_get_be32s(f, &s->irq_enabled); qemu_get_be32s(f, &s->reset3); qemu_get_be32s(f, &s->snapshot); return 0; }
/* This function is only used for old state version 1 and 2 */ static int apic_load_old(QEMUFile *f, void *opaque, int version_id) { APICCommonState *s = opaque; APICCommonClass *info = APIC_COMMON_GET_CLASS(s); int i; if (version_id > 2) { return -EINVAL; } /* XXX: what if the base changes? (registered memory regions) */ qemu_get_be32s(f, &s->apicbase); qemu_get_8s(f, &s->id); qemu_get_8s(f, &s->arb_id); qemu_get_8s(f, &s->tpr); qemu_get_be32s(f, &s->spurious_vec); qemu_get_8s(f, &s->log_dest); qemu_get_8s(f, &s->dest_mode); for (i = 0; i < 8; i++) { qemu_get_be32s(f, &s->isr[i]); qemu_get_be32s(f, &s->tmr[i]); qemu_get_be32s(f, &s->irr[i]); } for (i = 0; i < APIC_LVT_NB; i++) { qemu_get_be32s(f, &s->lvt[i]); } qemu_get_be32s(f, &s->esr); qemu_get_be32s(f, &s->icr[0]); qemu_get_be32s(f, &s->icr[1]); qemu_get_be32s(f, &s->divide_conf); s->count_shift = qemu_get_be32(f); qemu_get_be32s(f, &s->initial_count); s->initial_count_load_time = qemu_get_be64(f); s->next_time = qemu_get_be64(f); if (version_id >= 2) { s->timer_expiry = qemu_get_be64(f); } if (info->post_load) { info->post_load(s); } return 0; }
static int get_uint32(QEMUFile *f, void *pv, size_t size) { uint32_t *v = pv; qemu_get_be32s(f, v); return 0; }
int cpu_load(QEMUFile *f, void *opaque, int version_id) { CPUSPARCState *env = opaque; SPARCCPU *cpu = sparc_env_get_cpu(env); int i; uint32_t tmp; if (version_id < 6) return -EINVAL; for(i = 0; i < 8; i++) qemu_get_betls(f, &env->gregs[i]); qemu_get_be32s(f, &env->nwindows); for(i = 0; i < env->nwindows * 16; i++) qemu_get_betls(f, &env->regbase[i]); /* FPU */ for (i = 0; i < TARGET_DPREGS; i++) { env->fpr[i].l.upper = qemu_get_be32(f); env->fpr[i].l.lower = qemu_get_be32(f); } qemu_get_betls(f, &env->pc); qemu_get_betls(f, &env->npc); qemu_get_betls(f, &env->y); tmp = qemu_get_be32(f); env->cwp = 0; /* needed to ensure that the wrapping registers are correctly updated */ cpu_put_psr(env, tmp); qemu_get_betls(f, &env->fsr); qemu_get_betls(f, &env->tbr); tmp = qemu_get_be32(f); env->interrupt_index = tmp; qemu_get_be32s(f, &env->pil_in); #ifndef TARGET_SPARC64 qemu_get_be32s(f, &env->wim); /* MMU */ for (i = 0; i < 32; i++) qemu_get_be32s(f, &env->mmuregs[i]); for (i = 0; i < 4; i++) { qemu_get_be64s(f, &env->mxccdata[i]); } for (i = 0; i < 8; i++) { qemu_get_be64s(f, &env->mxccregs[i]); } qemu_get_be32s(f, &env->mmubpctrv); qemu_get_be32s(f, &env->mmubpctrc); qemu_get_be32s(f, &env->mmubpctrs); qemu_get_be64s(f, &env->mmubpaction); for (i = 0; i < 4; i++) { qemu_get_be64s(f, &env->mmubpregs[i]); } #else qemu_get_be64s(f, &env->lsu); for (i = 0; i < 16; i++) { qemu_get_be64s(f, &env->immuregs[i]); qemu_get_be64s(f, &env->dmmuregs[i]); } for (i = 0; i < 64; i++) { qemu_get_be64s(f, &env->itlb[i].tag); qemu_get_be64s(f, &env->itlb[i].tte); qemu_get_be64s(f, &env->dtlb[i].tag); qemu_get_be64s(f, &env->dtlb[i].tte); } qemu_get_be32s(f, &env->mmu_version); for (i = 0; i < MAXTL_MAX; i++) { qemu_get_be64s(f, &env->ts[i].tpc); qemu_get_be64s(f, &env->ts[i].tnpc); qemu_get_be64s(f, &env->ts[i].tstate); qemu_get_be32s(f, &env->ts[i].tt); } qemu_get_be32s(f, &env->xcc); qemu_get_be32s(f, &env->asi); qemu_get_be32s(f, &env->pstate); qemu_get_be32s(f, &env->tl); qemu_get_be32s(f, &env->cansave); qemu_get_be32s(f, &env->canrestore); qemu_get_be32s(f, &env->otherwin); qemu_get_be32s(f, &env->wstate); qemu_get_be32s(f, &env->cleanwin); for (i = 0; i < 8; i++) qemu_get_be64s(f, &env->agregs[i]); for (i = 0; i < 8; i++) qemu_get_be64s(f, &env->bgregs[i]); for (i = 0; i < 8; i++) qemu_get_be64s(f, &env->igregs[i]); for (i = 0; i < 8; i++) qemu_get_be64s(f, &env->mgregs[i]); qemu_get_be64s(f, &env->fprs); qemu_get_be64s(f, &env->tick_cmpr); qemu_get_be64s(f, &env->stick_cmpr); cpu_get_timer(f, env->tick); cpu_get_timer(f, env->stick); qemu_get_be64s(f, &env->gsr); qemu_get_be32s(f, &env->gl); qemu_get_be64s(f, &env->hpstate); for (i = 0; i < MAXTL_MAX; i++) qemu_get_be64s(f, &env->htstate[i]); qemu_get_be64s(f, &env->hintp); qemu_get_be64s(f, &env->htba); qemu_get_be64s(f, &env->hver); qemu_get_be64s(f, &env->hstick_cmpr); qemu_get_be64s(f, &env->ssr); cpu_get_timer(f, env->hstick); #endif tlb_flush(CPU(cpu), 1); return 0; }