/* Send the packet currently in the TX FIFO */
static void stellaris_enet_send(stellaris_enet_state *s)
{
int framelen = stellaris_txpacket_datalen(s);
/* Ethernet header is in the FIFO but not in the datacount.
* We don't implement explicit CRC, so just ignore any
* CRC value in the FIFO.
*/
framelen += 14;
if ((s->tctl & SE_TCTL_PADEN) && framelen < 60) {
memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen);
framelen = 60;
}
/* This MIN will have no effect unless the FIFO data is corrupt
* (eg bad data from an incoming migration); otherwise the check
* on the datalen at the start of writing the data into the FIFO
* will have caught this. Silently write a corrupt half-packet,
* which is what the hardware does in FIFO underrun situations.
*/
framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2);
qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen);
s->tx_fifo_len = 0;
s->ris |= SE_INT_TXEMP;
stellaris_enet_update(s);
DPRINTF("Done TX\n");
}
static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop)
{
struct fs_eth *eth = opaque;
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
qemu_send_packet(ð->nic->nc, buf, len);
return len;
}
static int eth_tx_push(void *opaque, unsigned char *buf, int len, bool eop)
{
ETRAXFSEthState *eth = opaque;
D(printf("%s buf=%p len=%d\n", __func__, buf, len));
qemu_send_packet(qemu_get_queue(eth->nic), buf, len);
return len;
}
/* Flush the TX FIFO. */
static void smc91c111_do_tx(smc91c111_state *s)
{
int i;
int len;
int control;
int packetnum;
uint8_t *p;
if ((s->tcr & TCR_TXEN) == 0)
return;
if (s->tx_fifo_len == 0)
return;
for (i = 0; i < s->tx_fifo_len; i++) {
packetnum = s->tx_fifo[i];
p = &s->data[packetnum][0];
/* Set status word. */
*(p++) = 0x01;
*(p++) = 0x40;
len = *(p++);
len |= ((int)*(p++)) << 8;
len -= 6;
control = p[len + 1];
if (control & 0x20)
len++;
/* ??? This overwrites the data following the buffer.
Don't know what real hardware does. */
if (len < 64 && (s->tcr & TCR_PAD_EN)) {
memset(p + len, 0, 64 - len);
len = 64;
}
#if 0
{
int add_crc;
/* The card is supposed to append the CRC to the frame.
However none of the other network traffic has the CRC
appended. Suspect this is low level ethernet detail we
don't need to worry about. */
add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
if (add_crc) {
uint32_t crc;
crc = crc32(~0, p, len);
memcpy(p + len, &crc, 4);
len += 4;
}
}
#endif
if (s->ctr & CTR_AUTO_RELEASE)
/* Race? */
smc91c111_release_packet(s, packetnum);
else if (s->tx_fifo_done_len < NUM_PACKETS)
s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
qemu_send_packet(&s->nic->nc, p, len);
}
s->tx_fifo_len = 0;
smc91c111_update(s);
}
static void ftgmac100_do_tx(Ftgmac100State *s)
{
int frame_size = 0;
uint8_t frame[FTGMAC100_MAX_FRAME_SIZE(s)];
uint8_t *ptr = frame;
uint32_t addr;
addr = ftgmac100_find_txdes(s, s->tx_descriptor);
while (1) {
Ftgmac100Desc bd;
int len;
ftgmac100_read_bd(&bd, addr);
if ((bd.des0 & FTGMAC100_TXDES0_TXDMA_OWN) == 0) {
/* Run out of descriptors to transmit. */
s->isr |= FTGMAC100_INT_NO_NPTXBUF;
break;
}
len = bd.des0 & 0x3FFF;
if (frame_size + len > FTGMAC100_MAX_FRAME_SIZE(s)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: frame too big : %d bytes\n",
__func__, len);
len = FTGMAC100_MAX_FRAME_SIZE(s) - frame_size;
}
dma_memory_read(&address_space_memory, bd.des3, ptr, len);
ptr += len;
frame_size += len;
if (bd.des0 & FTGMAC100_TXDES0_LTS) {
/* Last buffer in frame. */
qemu_send_packet(qemu_get_queue(s->nic), frame, len);
ptr = frame;
frame_size = 0;
if (bd.des1 & FTGMAC100_TXDES1_TXIC) {
s->isr |= FTGMAC100_INT_XPKT_ETH;
}
}
if (bd.des1 & FTGMAC100_TXDES1_TX2FIC) {
s->isr |= FTGMAC100_INT_XPKT_FIFO;
}
bd.des0 &= ~FTGMAC100_TXDES0_TXDMA_OWN;
/* Write back the modified descriptor. */
ftgmac100_write_bd(&bd, addr);
/* Advance to the next descriptor. */
if (bd.des0 & ftgmac100_txdes0_edotr(s)) {
addr = s->tx_ring;
} else {
addr += sizeof(Ftgmac100Desc);
}
}
s->tx_descriptor = addr;
ftgmac100_update_irq(s);
}
static void
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
uint32_t value = val64;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->regs[addr] = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_RX_CTRL0:
case R_RX_CTRL1:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
/* fall through */
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
default:
s->regs[addr] = tswap32(value);
break;
}
}
static void vde_to_qemu(void *opaque)
{
VDEState *s = opaque;
uint8_t buf[NET_BUFSIZE];
int size;
size = vde_recv(s->vde, (char *)buf, sizeof(buf), 0);
if (size > 0) {
qemu_send_packet(&s->nc, buf, size);
}
}
static void tap_win32_send(void *opaque)
{
TAPState *s = opaque;
uint8_t *buf;
int max_size = 4096;
int size;
size = tap_win32_read(s->handle, &buf, max_size);
if (size > 0) {
qemu_send_packet(&s->nc, buf, size);
tap_win32_free_buffer(s->handle, buf);
}
}
static void smc91c111_do_tx(smc91c111_state *s)
{
int i;
int len;
int control;
int add_crc;
int packetnum;
uint8_t *p;
if ((s->tcr & TCR_TXEN) == 0)
return;
if (s->tx_fifo_len == 0)
return;
for (i = 0; i < s->tx_fifo_len; i++) {
packetnum = s->tx_fifo[i];
p = &s->data[packetnum][0];
*(p++) = 0x01;
*(p++) = 0x40;
len = *(p++);
len |= ((int)*(p++)) << 8;
len -= 6;
control = p[len + 1];
if (control & 0x20)
len++;
if (len < 64 && (s->tcr & TCR_PAD_EN)) {
memset(p + len, 0, 64 - len);
len = 64;
}
#if 0
add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0;
if (add_crc) {
uint32_t crc;
crc = crc32(~0, p, len);
memcpy(p + len, &crc, 4);
len += 4;
}
#else
add_crc = 0;
#endif
if (s->ctr & CTR_AUTO_RELEASE)
smc91c111_release_packet(s, packetnum);
else if (s->tx_fifo_done_len < NUM_PACKETS)
s->tx_fifo_done[s->tx_fifo_done_len++] = packetnum;
qemu_send_packet(s->vc, p, len);
}
s->tx_fifo_len = 0;
smc91c111_update(s);
}
static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
MIPSnetState *s = opaque;
addr &= 0x3f;
#ifdef DEBUG_MIPSNET_DATA
printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
#endif
switch (addr) {
case MIPSNET_TX_DATA_COUNT:
s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
s->tx_written = 0;
break;
case MIPSNET_INT_CTL:
if (val & MIPSNET_INTCTL_TXDONE) {
s->intctl &= ~MIPSNET_INTCTL_TXDONE;
} else if (val & MIPSNET_INTCTL_RXDONE) {
s->intctl &= ~MIPSNET_INTCTL_RXDONE;
} else if (val & MIPSNET_INTCTL_TESTBIT) {
mipsnet_reset(s);
s->intctl |= MIPSNET_INTCTL_TESTBIT;
} else if (!val) {
/* ACK testbit interrupt, flag was cleared on read. */
}
s->busy = !!s->intctl;
mipsnet_update_irq(s);
break;
case MIPSNET_TX_DATA_BUFFER:
s->tx_buffer[s->tx_written++] = val;
if (s->tx_written == s->tx_count) {
/* Send buffer. */
#ifdef DEBUG_MIPSNET_SEND
printf("mipsnet: sending len=%d\n", s->tx_count);
#endif
qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
s->tx_count = s->tx_written = 0;
s->intctl |= MIPSNET_INTCTL_TXDONE;
s->busy = 1;
mipsnet_update_irq(s);
}
break;
/* Read-only registers */
case MIPSNET_DEV_ID:
case MIPSNET_BUSY:
case MIPSNET_RX_DATA_COUNT:
case MIPSNET_INTERRUPT_INFO:
case MIPSNET_RX_DATA_BUFFER:
default:
break;
}
}
static void
eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(&s->nic->nc,
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->regs[addr] = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
case R_RX_CTRL0:
case R_RX_CTRL1:
D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value));
s->regs[addr] = value;
break;
/* Packet data, make sure it stays BE. */
default:
s->regs[addr] = cpu_to_be32(value);
break;
}
}
static void net_socket_send_dgram(void *opaque)
{
NetSocketState *s = opaque;
int size;
size = qemu_recv(s->fd, s->buf, sizeof(s->buf), 0);
if (size < 0)
return;
if (size == 0) {
/* end of connection */
qemu_set_fd_handler(s->fd, NULL, NULL, NULL);
return;
}
qemu_send_packet(&s->nc, s->buf, size);
}
static void mipsnet_ioport_write(void *opaque, hwaddr addr,
uint64_t val, unsigned int size)
{
MIPSnetState *s = opaque;
addr &= 0x3f;
trace_mipsnet_write(addr, val);
switch (addr) {
case MIPSNET_TX_DATA_COUNT:
s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
s->tx_written = 0;
break;
case MIPSNET_INT_CTL:
if (val & MIPSNET_INTCTL_TXDONE) {
s->intctl &= ~MIPSNET_INTCTL_TXDONE;
} else if (val & MIPSNET_INTCTL_RXDONE) {
s->intctl &= ~MIPSNET_INTCTL_RXDONE;
} else if (val & MIPSNET_INTCTL_TESTBIT) {
mipsnet_reset(s);
s->intctl |= MIPSNET_INTCTL_TESTBIT;
} else if (!val) {
/* ACK testbit interrupt, flag was cleared on read. */
}
s->busy = !!s->intctl;
mipsnet_update_irq(s);
break;
case MIPSNET_TX_DATA_BUFFER:
s->tx_buffer[s->tx_written++] = val;
if (s->tx_written == s->tx_count) {
/* Send buffer. */
trace_mipsnet_send(s->tx_count);
qemu_send_packet(&s->nic->nc, s->tx_buffer, s->tx_count);
s->tx_count = s->tx_written = 0;
s->intctl |= MIPSNET_INTCTL_TXDONE;
s->busy = 1;
mipsnet_update_irq(s);
}
break;
/* Read-only registers */
case MIPSNET_DEV_ID:
case MIPSNET_BUSY:
case MIPSNET_RX_DATA_COUNT:
case MIPSNET_INTERRUPT_INFO:
case MIPSNET_RX_DATA_BUFFER:
default:
break;
}
}
static void
eth_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
unsigned int base = 0;
uint32_t value = val64;
addr >>= 2;
switch (addr)
{
case R_TX_CTRL0:
case R_TX_CTRL1:
if (addr == R_TX_CTRL1)
base = 0x800 / 4;
D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
__func__, addr * 4, value));
if ((value & (CTRL_P | CTRL_S)) == CTRL_S) {
qemu_send_packet(qemu_get_queue(s->nic),
(void *) &s->regs[base],
s->regs[base + R_TX_LEN0]);
D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0]));
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
} else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) {
memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6);
if (s->regs[base + R_TX_CTRL0] & CTRL_I)
eth_pulse_irq(s);
}
/* We are fast and get ready pretty much immediately so
we actually never flip the S nor P bits to one. */
s->regs[addr] = value & ~(CTRL_P | CTRL_S);
break;
/* Keep these native. */
case R_RX_CTRL0:
case R_RX_CTRL1:
if (!(value & CTRL_S)) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
case R_TX_LEN0:
case R_TX_LEN1:
case R_TX_GIE0:
D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n",
__func__, addr * 4, value));
s->regs[addr] = value;
break;
case R_MDIOCTRL:
if (((unsigned int)value & R_MDIOCTRL_MDIOSTS_MASK) != 0) {
struct TEMAC *t = &s->TEMAC;
unsigned int op = s->regs[R_MDIOADDR] & R_MDIOADDR_OP_MASK;
unsigned int phyaddr = (s->regs[R_MDIOADDR] &
R_MDIOADDR_PHYADR_MASK) >> R_MDIOADDR_PHYADR_SHIFT;
unsigned int regaddr = s->regs[R_MDIOADDR] &
R_MDIOADDR_REGADR_MASK;
if (op) {
/* read PHY registers */
s->regs[R_MDIORD] = mdio_read_req(
&t->mdio_bus, phyaddr, regaddr);
} else {
/* write PHY registers */
mdio_write_req(&t->mdio_bus, phyaddr, regaddr,
s->regs[R_MDIOWR]);
}
}
s->regs[addr] = value;
default:
s->regs[addr] = tswap32(value);
break;
}
}
static target_ulong h_send_logical_lan(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
target_ulong *bufs = args + 1;
target_ulong continue_token = args[7];
VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
VIOsPAPRVLANDevice *dev = VIO_SPAPR_VLAN_DEVICE(sdev);
unsigned total_len;
uint8_t *lbuf, *p;
int i, nbufs;
int ret;
trace_spapr_vlan_h_send_logical_lan(reg, continue_token);
if (!sdev) {
return H_PARAMETER;
}
trace_spapr_vlan_h_send_logical_lan_rxbufs(dev->rx_bufs);
if (!dev->isopen) {
return H_DROPPED;
}
if (continue_token) {
return H_HARDWARE; /* FIXME actually handle this */
}
total_len = 0;
for (i = 0; i < 6; i++) {
trace_spapr_vlan_h_send_logical_lan_buf_desc(bufs[i]);
if (!(bufs[i] & VLAN_BD_VALID)) {
break;
}
total_len += VLAN_BD_LEN(bufs[i]);
}
nbufs = i;
trace_spapr_vlan_h_send_logical_lan_total(nbufs, total_len);
if (total_len == 0) {
return H_SUCCESS;
}
if (total_len > MAX_PACKET_SIZE) {
/* Don't let the guest force too large an allocation */
return H_RESOURCE;
}
lbuf = alloca(total_len);
p = lbuf;
for (i = 0; i < nbufs; i++) {
ret = spapr_vio_dma_read(sdev, VLAN_BD_ADDR(bufs[i]),
p, VLAN_BD_LEN(bufs[i]));
if (ret < 0) {
return ret;
}
p += VLAN_BD_LEN(bufs[i]);
}
qemu_send_packet(qemu_get_queue(dev->nic), lbuf, total_len);
return H_SUCCESS;
}
static target_ulong h_send_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr,
target_ulong opcode, target_ulong *args)
{
target_ulong reg = args[0];
target_ulong *bufs = args + 1;
target_ulong continue_token = args[7];
VIOsPAPRDevice *sdev = spapr_vio_find_by_reg(spapr->vio_bus, reg);
VIOsPAPRVLANDevice *dev = (VIOsPAPRVLANDevice *)sdev;
unsigned total_len;
uint8_t *lbuf, *p;
int i, nbufs;
int ret;
dprintf("H_SEND_LOGICAL_LAN(0x" TARGET_FMT_lx ", <bufs>, 0x"
TARGET_FMT_lx ")\n", reg, continue_token);
if (!sdev) {
return H_PARAMETER;
}
dprintf("rxbufs = %d\n", dev->rx_bufs);
if (!dev->isopen) {
return H_DROPPED;
}
if (continue_token) {
return H_HARDWARE; /* FIXME actually handle this */
}
total_len = 0;
for (i = 0; i < 6; i++) {
dprintf(" buf desc: 0x" TARGET_FMT_lx "\n", bufs[i]);
if (!(bufs[i] & VLAN_BD_VALID)) {
break;
}
total_len += VLAN_BD_LEN(bufs[i]);
}
nbufs = i;
dprintf("h_send_logical_lan() %d buffers, total length 0x%x\n",
nbufs, total_len);
if (total_len == 0) {
return H_SUCCESS;
}
if (total_len > MAX_PACKET_SIZE) {
/* Don't let the guest force too large an allocation */
return H_RESOURCE;
}
lbuf = alloca(total_len);
p = lbuf;
for (i = 0; i < nbufs; i++) {
ret = spapr_vio_dma_read(sdev, VLAN_BD_ADDR(bufs[i]),
p, VLAN_BD_LEN(bufs[i]));
if (ret < 0) {
return ret;
}
p += VLAN_BD_LEN(bufs[i]);
}
qemu_send_packet(&dev->nic->nc, lbuf, total_len);
return H_SUCCESS;
}
static void net_tx_packets(struct XenNetDev *netdev)
{
netif_tx_request_t txreq;
RING_IDX rc, rp;
void *page;
void *tmpbuf = NULL;
for (;;) {
rc = netdev->tx_ring.req_cons;
rp = netdev->tx_ring.sring->req_prod;
xen_rmb(); /* Ensure we see queued requests up to 'rp'. */
while ((rc != rp)) {
if (RING_REQUEST_CONS_OVERFLOW(&netdev->tx_ring, rc)) {
break;
}
memcpy(&txreq, RING_GET_REQUEST(&netdev->tx_ring, rc), sizeof(txreq));
netdev->tx_ring.req_cons = ++rc;
#if 1
/* should not happen in theory, we don't announce the *
* feature-{sg,gso,whatelse} flags in xenstore (yet?) */
if (txreq.flags & NETTXF_extra_info) {
xen_be_printf(&netdev->xendev, 0, "FIXME: extra info flag\n");
net_tx_error(netdev, &txreq, rc);
continue;
}
if (txreq.flags & NETTXF_more_data) {
xen_be_printf(&netdev->xendev, 0, "FIXME: more data flag\n");
net_tx_error(netdev, &txreq, rc);
continue;
}
#endif
if (txreq.size < 14) {
xen_be_printf(&netdev->xendev, 0, "bad packet size: %d\n", txreq.size);
net_tx_error(netdev, &txreq, rc);
continue;
}
if ((txreq.offset + txreq.size) > XC_PAGE_SIZE) {
xen_be_printf(&netdev->xendev, 0, "error: page crossing\n");
net_tx_error(netdev, &txreq, rc);
continue;
}
xen_be_printf(&netdev->xendev, 3, "tx packet ref %d, off %d, len %d, flags 0x%x%s%s%s%s\n",
txreq.gref, txreq.offset, txreq.size, txreq.flags,
(txreq.flags & NETTXF_csum_blank) ? " csum_blank" : "",
(txreq.flags & NETTXF_data_validated) ? " data_validated" : "",
(txreq.flags & NETTXF_more_data) ? " more_data" : "",
(txreq.flags & NETTXF_extra_info) ? " extra_info" : "");
page = xc_gnttab_map_grant_ref(netdev->xendev.gnttabdev,
netdev->xendev.dom,
txreq.gref, PROT_READ);
if (page == NULL) {
xen_be_printf(&netdev->xendev, 0, "error: tx gref dereference failed (%d)\n",
txreq.gref);
net_tx_error(netdev, &txreq, rc);
continue;
}
if (txreq.flags & NETTXF_csum_blank) {
/* have read-only mapping -> can't fill checksum in-place */
if (!tmpbuf) {
tmpbuf = g_malloc(XC_PAGE_SIZE);
}
memcpy(tmpbuf, page + txreq.offset, txreq.size);
net_checksum_calculate(tmpbuf, txreq.size);
qemu_send_packet(&netdev->nic->nc, tmpbuf, txreq.size);
} else {
qemu_send_packet(&netdev->nic->nc, page + txreq.offset, txreq.size);
}
xc_gnttab_munmap(netdev->xendev.gnttabdev, page, 1);
net_tx_response(netdev, &txreq, NETIF_RSP_OKAY);
}
if (!netdev->tx_work) {
break;
}
netdev->tx_work = 0;
}
g_free(tmpbuf);
}
static void net_socket_send(void *opaque)
{
NetSocketState *s = opaque;
int size, err;
unsigned l;
uint8_t buf1[4096];
const uint8_t *buf;
size = qemu_recv(s->fd, buf1, sizeof(buf1), 0);
if (size < 0) {
err = socket_error();
if (err != EWOULDBLOCK)
goto eoc;
} else if (size == 0) {
/* end of connection */
eoc:
qemu_set_fd_handler(s->fd, NULL, NULL, NULL);
if (s->listen_fd != -1) {
qemu_set_fd_handler(s->listen_fd, net_socket_accept, NULL, s);
}
closesocket(s->fd);
s->fd = -1;
s->state = 0;
s->index = 0;
s->packet_len = 0;
s->nc.link_down = true;
memset(s->buf, 0, sizeof(s->buf));
memset(s->nc.info_str, 0, sizeof(s->nc.info_str));
return;
}
buf = buf1;
while (size > 0) {
/* reassemble a packet from the network */
switch(s->state) {
case 0:
l = 4 - s->index;
if (l > size)
l = size;
memcpy(s->buf + s->index, buf, l);
buf += l;
size -= l;
s->index += l;
if (s->index == 4) {
/* got length */
s->packet_len = ntohl(*(uint32_t *)s->buf);
s->index = 0;
s->state = 1;
}
break;
case 1:
l = s->packet_len - s->index;
if (l > size)
l = size;
if (s->index + l <= sizeof(s->buf)) {
memcpy(s->buf + s->index, buf, l);
} else {
fprintf(stderr, "serious error: oversized packet received,"
"connection terminated.\n");
s->state = 0;
goto eoc;
}
s->index += l;
buf += l;
size -= l;
if (s->index >= s->packet_len) {
qemu_send_packet(&s->nc, s->buf, s->packet_len);
s->index = 0;
s->state = 0;
}
break;
}
}
}
static void dp8393x_do_transmit_packets(dp8393xState *s)
{
NetClientState *nc = qemu_get_queue(s->nic);
uint16_t data[12];
int width, size;
int tx_len, len;
uint16_t i;
width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
while (1) {
/* Read memory */
size = sizeof(uint16_t) * 6 * width;
s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
tx_len = 0;
/* Update registers */
s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
s->regs[SONIC_TPS] = data[1 * width];
s->regs[SONIC_TFC] = data[2 * width];
s->regs[SONIC_TSA0] = data[3 * width];
s->regs[SONIC_TSA1] = data[4 * width];
s->regs[SONIC_TFS] = data[5 * width];
/* Handle programmable interrupt */
if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
} else {
s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
}
for (i = 0; i < s->regs[SONIC_TFC]; ) {
/* Append fragment */
len = s->regs[SONIC_TFS];
if (tx_len + len > sizeof(s->tx_buffer)) {
len = sizeof(s->tx_buffer) - tx_len;
}
address_space_rw(&s->as, dp8393x_tsa(s),
MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
tx_len += len;
i++;
if (i != s->regs[SONIC_TFC]) {
/* Read next fragment details */
size = sizeof(uint16_t) * 3 * width;
address_space_rw(&s->as,
dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_TSA0] = data[0 * width];
s->regs[SONIC_TSA1] = data[1 * width];
s->regs[SONIC_TFS] = data[2 * width];
}
}
/* Handle Ethernet checksum */
if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
/* Don't append FCS there, to look like slirp packets
* which don't have one */
} else {
/* Remove existing FCS */
tx_len -= 4;
}
if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
/* Loopback */
s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
if (nc->info->can_receive(nc)) {
s->loopback_packet = 1;
nc->info->receive(nc, s->tx_buffer, tx_len);
}
} else {
/* Transmit packet */
qemu_send_packet(nc, s->tx_buffer, tx_len);
}
s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
/* Write status */
data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
dp8393x_ttda(s),
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
/* Read footer of packet */
size = sizeof(uint16_t) * width;
address_space_rw(&s->as,
dp8393x_ttda(s) +
sizeof(uint16_t) *
(4 + 3 * s->regs[SONIC_TFC]) * width,
MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
if (data[0 * width] & 0x1) {
/* EOL detected */
break;
}
}
}
/* Done */
s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
dp8393x_update_irq(s);
}
