static void quark_usb_init(void) { u32 bar; /* Change USB EHCI packet buffer OUT/IN threshold */ qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); /* Disable USB device interrupts */ qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); writel(0x7f, bar + USBD_INT_MASK); writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); }
/* * Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin. * * We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this * pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata() * in the Intel ICH6 GPIO driver where it calls PCI configuration space access * APIs which will trigger PCI enumeration process. * * Check <asm/arch-quark/quark.h> for more details. */ void board_assert_perst(void) { u32 base, port, val; /* retrieve the GPIO IO base */ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); base = (base & 0xffff) & ~0x7f; /* enable the pin */ port = base + 0x20; val = inl(port); val |= (1 << 0); outl(val, port); /* configure the pin as output */ port = base + 0x24; val = inl(port); val &= ~(1 << 0); outl(val, port); /* pull it down (assert) */ port = base + 0x28; val = inl(port); val &= ~(1 << 0); outl(val, port); }
/* * TODO: * * This whole routine should be removed until we fully convert the ICH SPI * driver to DM and make use of DT to pass the bios control register offset */ static void unprotect_spi_flash(void) { u32 bc; qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc); bc |= 0x1; /* unprotect the flash */ qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc); }
static void quark_pcie_init(void) { u32 val; /* PCIe upstream non-posted & posted request size */ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG, CCFG_UPRS | CCFG_UNRS); qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG, CCFG_UPRS | CCFG_UNRS); /* PCIe packet fast transmit mode (IPF) */ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF); qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF); /* PCIe message bus idle counter (SBIC) */ qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val); val |= MBC_SBIC; qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val); qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val); val |= MBC_SBIC; qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val); }
void board_deassert_perst(void) { u32 base, port, val; /* retrieve the GPIO IO base */ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, PCI_CFG_GPIOBASE, &base); base = (base & 0xffff) & ~0x7f; /* pull it up (de-assert) */ port = base + 0x28; val = inl(port); val |= (1 << 0); outl(val, port); }
void board_final_cleanup(void) { struct quark_rcba *rcba; u32 base, val; qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); base &= ~MEM_BAR_EN; rcba = (struct quark_rcba *)base; /* Initialize 'Component ID' to zero */ val = readl(&rcba->esd); val &= ~0xff0000; writel(val, &rcba->esd); /* Lock HMBOUND for security */ msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK); return; }
static void quark_irq_init(void) { struct quark_rcba *rcba; u32 base; qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base); base &= ~MEM_BAR_EN; rcba = (struct quark_rcba *)base; /* * Route Quark PCI device interrupt pin to PIRQ * * Route device#23's INTA/B/C/D to PIRQA/B/C/D * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H */ writew(PIRQC, &rcba->rmu_ir); writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), &rcba->d23_ir); writew(PIRQD, &rcba->core_ir); writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), &rcba->d20d21_ir); }