// // Interrupt processing // static void quicc_eth_int(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct scc_regs *scc = qi->ctl; unsigned short scce; qi->interrupts++; while ( (scce = scc->scc_scce) != 0 ) { scc->scc_scce = scce; if ( (scce & (QUICC_SCCE_TXE | QUICC_SCCE_TX)) != 0) { quicc_eth_TxEvent(sc, scce); } if ( (scce & ( QUICC_SCCE_RXF | QUICC_SCCE_RX )) != 0) { quicc_eth_RxEvent(sc); } if ( (scce & QUICC_SCCE_BSY) != 0) { qi->rx_resource_errors++; } if ( (scce & QUICC_SCCE_GRC) != 0 ) { quicc_eth_command(sc, QUICC_CPM_CR_RESTART_TX); qi->tx_restart++; quicc_eth_command(sc, QUICC_CPM_CR_HUNT_MODE); qi->rx_restart++; } } }
// // Interrupt processing // static void quicc_eth_int(struct eth_drv_sc *sc) { struct quicc_eth_info *qi = (struct quicc_eth_info *)sc->driver_private; volatile struct scc_regs *scc = qi->ctl; unsigned short scce; while ((scce = (scc->scc_scce & QUICC_SCCE_INTS)) != 0) { if ((scce & (QUICC_SCCE_TXE | QUICC_SCCE_TX)) != 0) { quicc_eth_TxEvent(sc, scce); } if ((scce & QUICC_SCCE_RXF) != 0) { quicc_eth_RxEvent(sc); } scc->scc_scce = scce; // Reset the bits we handled } }