irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) { struct drm_device *dev = (struct drm_device *) arg; struct radeon_device *rdev = dev->dev_private; return radeon_irq_process(rdev); }
/** * radeon_driver_irq_handler_kms - irq handler for KMS * * @int irq, void *arg: args * * This is the irq handler for the radeon KMS driver (all asics). * radeon_irq_process is a macro that points to the per-asic * irq handler callback. */ irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct radeon_device *rdev = dev->dev_private; irqreturn_t ret; ret = radeon_irq_process(rdev); if (ret == IRQ_HANDLED) pm_runtime_mark_last_busy(dev->dev); return ret; }
/** * radeon_driver_irq_handler_kms - irq handler for KMS * * @DRM_IRQ_ARGS: args * * This is the irq handler for the radeon KMS driver (all asics). * radeon_irq_process is a macro that points to the per-asic * irq handler callback. */ int radeon_driver_irq_handler_kms(void *arg) { struct drm_device *dev = arg; struct radeon_device *rdev = dev->dev_private; if (!rdev->irq.installed) return (0); return radeon_irq_process(rdev); }
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; /* Disable *all* interrupts */ rdev->irq.sw_int = false; for (i = 0; i < 2; i++) { rdev->irq.crtc_vblank_int[i] = false; } radeon_irq_set(rdev); /* Clear bits */ radeon_irq_process(rdev); }
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; rdev->irq.sw_int = false; for (i = 0; i < 2; i++) { rdev->irq.crtc_vblank_int[i] = false; } radeon_irq_set(rdev); radeon_irq_process(rdev); }
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; /* Disable *all* interrupts */ rdev->irq.sw_int = false; rdev->irq.gui_idle = false; for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; for (i = 0; i < RADEON_MAX_CRTCS; i++) { rdev->irq.crtc_vblank_int[i] = false; rdev->irq.pflip[i] = false; } radeon_irq_set(rdev); /* Clear bits */ radeon_irq_process(rdev); }
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func); /* Disable *all* interrupts */ rdev->irq.sw_int = false; rdev->irq.gui_idle = false; for (i = 0; i < rdev->num_crtc; i++) rdev->irq.crtc_vblank_int[i] = false; for (i = 0; i < 6; i++) rdev->irq.hpd[i] = false; radeon_irq_set(rdev); /* Clear bits */ radeon_irq_process(rdev); }
void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; for (i = 0; i < RADEON_NUM_RINGS; i++) rdev->irq.sw_int[i] = false; rdev->irq.gui_idle = false; for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; for (i = 0; i < RADEON_MAX_CRTCS; i++) { rdev->irq.crtc_vblank_int[i] = false; rdev->irq.pflip[i] = false; } radeon_irq_set(rdev); radeon_irq_process(rdev); }
/** * radeon_driver_irq_preinstall_kms - drm irq preinstall callback * * @dev: drm dev pointer * * Gets the hw ready to enable irqs (all asics). * This function disables all interrupt sources on the GPU. */ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned i; lockmgr(&rdev->irq.lock, LK_EXCLUSIVE); /* Disable *all* interrupts */ for (i = 0; i < RADEON_NUM_RINGS; i++) atomic_set(&rdev->irq.ring_int[i], 0); for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; for (i = 0; i < RADEON_MAX_CRTCS; i++) { rdev->irq.crtc_vblank_int[i] = false; atomic_set(&rdev->irq.pflip[i], 0); rdev->irq.afmt[i] = false; } radeon_irq_set(rdev); lockmgr(&rdev->irq.lock, LK_RELEASE); /* Clear bits */ radeon_irq_process(rdev); }
/** * radeon_driver_irq_preinstall_kms - drm irq preinstall callback * * @dev: drm dev pointer * * Gets the hw ready to enable irqs (all asics). * This function disables all interrupt sources on the GPU. */ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned long irqflags; unsigned i; DRM_SPINLOCK_IRQSAVE(&rdev->irq.lock, irqflags); /* Disable *all* interrupts */ for (i = 0; i < RADEON_NUM_RINGS; i++) atomic_set(&rdev->irq.ring_int[i], 0); for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; for (i = 0; i < RADEON_MAX_CRTCS; i++) { rdev->irq.crtc_vblank_int[i] = false; atomic_set(&rdev->irq.pflip[i], 0); rdev->irq.afmt[i] = false; } radeon_irq_set(rdev); DRM_SPINUNLOCK_IRQRESTORE(&rdev->irq.lock, irqflags); /* Clear bits */ radeon_irq_process(rdev); }
/** * radeon_driver_irq_preinstall_kms - drm irq preinstall callback * * @dev: drm dev pointer * * Gets the hw ready to enable irqs (all asics). * This function disables all interrupt sources on the GPU. */ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; unsigned long irqflags; unsigned i; spin_lock_irqsave(&rdev->irq.lock, irqflags); /* Disable *all* interrupts */ for (i = 0; i < RADEON_NUM_RINGS; i++) atomic_set(&rdev->irq.ring_int[i], 0); rdev->irq.dpm_thermal = false; for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; for (i = 0; i < RADEON_MAX_CRTCS; i++) { rdev->irq.crtc_vblank_int[i] = false; atomic_set(&rdev->irq.pflip[i], 0); rdev->irq.afmt[i] = false; } radeon_irq_set(rdev); spin_unlock_irqrestore(&rdev->irq.lock, irqflags); /* Clear bits */ radeon_irq_process(rdev); }