int main(void) {
unsigned short addr1 = 0x1234; // the address for writing the ram
char data[] = "Help, I'm stuck in the RAM!"; // the test message
char read[] = "***************************"; // buffer for reading from ram
char buf[100]; // buffer for comm. with the user
unsigned char status; // used to verify we set the status
NU32_Startup(); // cache on, interrupts on, LED/button init, UART init
ram_init();
// check the ram status
CS = 0;
spi_io(0x5); // ram read status command
status = spi_io(0); // the actual status
CS = 1;
sprintf(buf, "Status 0x%x\r\n",status);
NU32_WriteUART3(buf);
sprintf(buf,"Writing \"%s\" to ram at address 0x%x\r\n", data, addr1);
NU32_WriteUART3(buf);
// write the data to the ram
ram_write(addr1, data, strlen(data) + 1); // +1, to send the '\0' character
ram_read(addr1, read, strlen(data) + 1); // read the data back
sprintf(buf,"Read \"%s\" from ram at address 0x%x\r\n", read, addr1);
NU32_WriteUART3(buf);
while(1) {
;
}
return 0;
}
int main(int argc, char **argv) {
int i;
ram_init();
cpu_reset();
load_rom("microwriter.rom");
for (i = 0; i < 10000; i++) {
cpu_cycle();
}
printf("Done.\n");
ram_free();
return 0;
}
static void sun4uv_init(MemoryRegion *address_space_mem,
ram_addr_t RAM_size,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
{
SPARCCPU *cpu;
M48t59State *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
ISABus *isa_bus;
qemu_irq *ivec_irqs, *pbm_irqs;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *fd[MAX_FD];
void *fw_cfg;
/* init CPUs */
cpu = cpu_devinit(cpu_model, hwdef);
/* set up devices */
ram_init(0, RAM_size);
prom_init(hwdef->prom_addr, bios_name);
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
&pci_bus3, &pbm_irqs);
pci_vga_init(pci_bus);
// XXX Should be pci_bus3
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {
if (serial_hds[i]) {
serial_isa_init(isa_bus, i, serial_hds[i]);
}
}
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
if (parallel_hds[i]) {
parallel_init(isa_bus, i, parallel_hds[i]);
}
}
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
ide_drive_get(hd, MAX_IDE_BUS);
pci_cmd646_ide_init(pci_bus, hd, 1);
isa_create_simple(isa_bus, "i8042");
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
fdctrl_init_isa(isa_bus, fd);
nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
kernel_addr, kernel_size,
kernel_cmdline,
initrd_addr, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&nd_table[0].macaddr);
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static int
nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
struct nouveau_clock *clk = nouveau_clock(pfb);
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nvc0_ram *ram = (void *)pfb->ram;
struct nvc0_ramfuc *fuc = &ram->fuc;
u8 ver, cnt, len, strap;
struct {
u32 data;
u8 size;
} rammap, ramcfg, timing;
int ref, div, out;
int from, mode;
int N1, M1, P;
int ret;
/* lookup memory config data relevant to the target frequency */
rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
&cnt, &ramcfg.size);
if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
nv_error(pfb, "invalid/missing rammap entry\n");
return -EINVAL;
}
/* locate specific data set for the attached memory */
strap = nvbios_ramcfg_index(nv_subdev(pfb));
if (strap >= cnt) {
nv_error(pfb, "invalid ramcfg strap\n");
return -EINVAL;
}
ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
nv_error(pfb, "invalid/missing ramcfg entry\n");
return -EINVAL;
}
/* lookup memory timings, if bios says they're present */
strap = nv_ro08(bios, ramcfg.data + 0x01);
if (strap != 0xff) {
timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
&cnt, &len);
if (!timing.data || ver != 0x10 || timing.size < 0x19) {
nv_error(pfb, "invalid/missing timing entry\n");
return -EINVAL;
}
} else {
timing.data = 0;
}
ret = ram_init(fuc, pfb);
if (ret)
return ret;
/* determine current mclk configuration */
from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */
/* determine target mclk configuration */
if (!(ram_rd32(fuc, 0x137300) & 0x00000100))
ref = clk->read(clk, nv_clk_src_sppll0);
else
ref = clk->read(clk, nv_clk_src_sppll1);
div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;
out = (ref * 2) / (div + 2);
mode = freq != out;
ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);
if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {
ram_nuke(fuc, 0x132000);
ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);
ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);
}
if (mode == 1) {
ram_nuke(fuc, 0x10fe20);
ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);
ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);
}
// 0x00020034 // 0x0000000a
ram_wr32(fuc, 0x132100, 0x00000001);
if (mode == 1 && from == 0) {
/* calculate refpll */
ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll,
ram->mempll.refclk, &N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
}
ram_wr32(fuc, 0x10fe20, 0x20010000);
ram_wr32(fuc, 0x137320, 0x00000003);
ram_wr32(fuc, 0x137330, 0x81200006);
ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);
ram_wr32(fuc, 0x10fe20, 0x20010001);
ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
/* calculate mempll */
ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq,
&N1, NULL, &M1, &P);
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return ret ? ret : -ERANGE;
}
ram_wr32(fuc, 0x10fe20, 0x20010005);
ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);
ram_wr32(fuc, 0x132000, 0x18010101);
ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
} else
if (mode == 0) {
ram_wr32(fuc, 0x137300, 0x00000003);
}
if (from == 0) {
ram_nuke(fuc, 0x10fb04);
ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);
ram_nuke(fuc, 0x10fb08);
ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);
ram_wr32(fuc, 0x10f988, 0x2004ff00);
ram_wr32(fuc, 0x10f98c, 0x003fc040);
ram_wr32(fuc, 0x10f990, 0x20012001);
ram_wr32(fuc, 0x10f998, 0x00011a00);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
} else {
ram_wr32(fuc, 0x10f988, 0x20010000);
ram_wr32(fuc, 0x10f98c, 0x00000000);
ram_wr32(fuc, 0x10f990, 0x20012001);
ram_wr32(fuc, 0x10f998, 0x00010a00);
}
if (from == 0) {
// 0x00020039 // 0x000000ba
}
// 0x0002003a // 0x00000002
ram_wr32(fuc, 0x100b0c, 0x00080012);
// 0x00030014 // 0x00000000 // 0x02b5f070
// 0x00030014 // 0x00010000 // 0x02b5f070
ram_wr32(fuc, 0x611200, 0x00003300);
// 0x00020034 // 0x0000000a
// 0x00030020 // 0x00000001 // 0x00000000
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
ram_wr32(fuc, 0x10f210, 0x00000000);
ram_nsec(fuc, 1000);
if (mode == 0)
nvc0_ram_train(fuc, 0x000c1001);
ram_wr32(fuc, 0x10f310, 0x00000001);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f090, 0x00000061);
ram_wr32(fuc, 0x10f090, 0xc000007f);
ram_nsec(fuc, 1000);
if (from == 0) {
ram_wr32(fuc, 0x10f824, 0x00007fd4);
} else {
ram_wr32(fuc, 0x1373ec, 0x00020404);
}
if (mode == 0) {
ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);
ram_wr32(fuc, 0x10f830, 0x41500010);
ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);
ram_wr32(fuc, 0x10f050, 0xff000090);
ram_wr32(fuc, 0x1373ec, 0x00020f0f);
ram_wr32(fuc, 0x1373f0, 0x00000003);
ram_wr32(fuc, 0x137310, 0x81201616);
ram_wr32(fuc, 0x132100, 0x00000001);
// 0x00020039 // 0x000000ba
ram_wr32(fuc, 0x10f830, 0x00300017);
ram_wr32(fuc, 0x1373f0, 0x00000001);
ram_wr32(fuc, 0x10f824, 0x00007e77);
ram_wr32(fuc, 0x132000, 0x18030001);
ram_wr32(fuc, 0x10f090, 0x4000007e);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f314, 0x00000001);
ram_wr32(fuc, 0x10f210, 0x80000000);
ram_wr32(fuc, 0x10f338, 0x00300220);
ram_wr32(fuc, 0x10f300, 0x0000011d);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f290, 0x02060505);
ram_wr32(fuc, 0x10f294, 0x34208288);
ram_wr32(fuc, 0x10f298, 0x44050411);
ram_wr32(fuc, 0x10f29c, 0x0000114c);
ram_wr32(fuc, 0x10f2a0, 0x42e10069);
ram_wr32(fuc, 0x10f614, 0x40044f77);
ram_wr32(fuc, 0x10f610, 0x40044f77);
ram_wr32(fuc, 0x10f344, 0x00600009);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f348, 0x00700008);
ram_wr32(fuc, 0x61c140, 0x19240000);
ram_wr32(fuc, 0x10f830, 0x00300017);
nvc0_ram_train(fuc, 0x80021001);
nvc0_ram_train(fuc, 0x80081001);
ram_wr32(fuc, 0x10f340, 0x00500004);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f830, 0x01300017);
ram_wr32(fuc, 0x10f830, 0x00300017);
// 0x00030020 // 0x00000000 // 0x00000000
// 0x00020034 // 0x0000000b
ram_wr32(fuc, 0x100b0c, 0x00080028);
ram_wr32(fuc, 0x611200, 0x00003330);
} else {
ram_wr32(fuc, 0x10f800, 0x00001800);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x1373ec, 0x00020404);
ram_wr32(fuc, 0x1373f0, 0x00000003);
ram_wr32(fuc, 0x10f830, 0x40700010);
ram_wr32(fuc, 0x10f830, 0x40500010);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x1373f8, 0x00000000);
ram_wr32(fuc, 0x132100, 0x00000101);
ram_wr32(fuc, 0x137310, 0x89201616);
ram_wr32(fuc, 0x10f050, 0xff000090);
ram_wr32(fuc, 0x1373ec, 0x00030404);
ram_wr32(fuc, 0x1373f0, 0x00000002);
// 0x00020039 // 0x00000011
ram_wr32(fuc, 0x132100, 0x00000001);
ram_wr32(fuc, 0x1373f8, 0x00002000);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f808, 0x7aaa0050);
ram_wr32(fuc, 0x10f830, 0x00500010);
ram_wr32(fuc, 0x10f200, 0x00ce1000);
ram_wr32(fuc, 0x10f090, 0x4000007e);
ram_nsec(fuc, 2000);
ram_wr32(fuc, 0x10f314, 0x00000001);
ram_wr32(fuc, 0x10f210, 0x80000000);
ram_wr32(fuc, 0x10f338, 0x00300200);
ram_wr32(fuc, 0x10f300, 0x0000084d);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f290, 0x0b343825);
ram_wr32(fuc, 0x10f294, 0x3483028e);
ram_wr32(fuc, 0x10f298, 0x440c0600);
ram_wr32(fuc, 0x10f29c, 0x0000214c);
ram_wr32(fuc, 0x10f2a0, 0x42e20069);
ram_wr32(fuc, 0x10f200, 0x00ce0000);
ram_wr32(fuc, 0x10f614, 0x60044e77);
ram_wr32(fuc, 0x10f610, 0x60044e77);
ram_wr32(fuc, 0x10f340, 0x00500000);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f344, 0x00600228);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f348, 0x00700000);
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x61c140, 0x09a40000);
nvc0_ram_train(fuc, 0x800e1008);
ram_nsec(fuc, 1000);
ram_wr32(fuc, 0x10f800, 0x00001804);
// 0x00030020 // 0x00000000 // 0x00000000
// 0x00020034 // 0x0000000b
ram_wr32(fuc, 0x13d8f4, 0x00000000);
ram_wr32(fuc, 0x100b0c, 0x00080028);
ram_wr32(fuc, 0x611200, 0x00003330);
ram_nsec(fuc, 100000);
ram_wr32(fuc, 0x10f9b0, 0x05313f41);
ram_wr32(fuc, 0x10f9b4, 0x00002f50);
nvc0_ram_train(fuc, 0x010c1001);
}
ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);
// 0x00020016 // 0x00000000
if (mode == 0)
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
return 0;
}
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
MachineState *machine)
{
const char *cpu_model = machine->cpu_model;
unsigned int i;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
qemu_irq esp_reset, dma_enable;
qemu_irq fdc_tc;
qemu_irq *cpu_halt;
unsigned long kernel_size;
DriveInfo *fd[MAX_FD];
FWCfgState *fw_cfg;
unsigned int num_vsimms;
/* init CPUs */
if (!cpu_model)
cpu_model = hwdef->default_cpu_model;
for(i = 0; i < smp_cpus; i++) {
cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
}
for (i = smp_cpus; i < MAX_CPUS; i++)
cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
/* set up devices */
ram_init(0, machine->ram_size, hwdef->max_mem);
/* models without ECC don't trap when missing ram is accessed */
if (!hwdef->ecc_base) {
empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
}
prom_init(hwdef->slavio_base, bios_name);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
cpu_irqs);
for (i = 0; i < 32; i++) {
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
}
for (i = 0; i < MAX_CPUS; i++) {
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
}
if (hwdef->idreg_base) {
idreg_init(hwdef->idreg_base);
}
if (hwdef->afx_base) {
afx_init(hwdef->afx_base);
}
iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
slavio_irq[30]);
if (hwdef->iommu_pad_base) {
/* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
Software shouldn't use aliased addresses, neither should it crash
when does. Using empty_slot instead of aliasing can help with
debugging such accesses */
empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
}
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
iommu, &espdma_irq, 0);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[16], iommu, &ledma_irq, 1);
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
exit (1);
}
num_vsimms = 0;
if (num_vsimms == 0) {
if (vga_interface_type == VGA_CG3) {
if (graphic_depth != 8) {
error_report("Unsupported depth: %d", graphic_depth);
exit(1);
}
if (!(graphic_width == 1024 && graphic_height == 768) &&
!(graphic_width == 1152 && graphic_height == 900)) {
error_report("Unsupported resolution: %d x %d", graphic_width,
graphic_height);
exit(1);
}
/* sbus irq 5 */
cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
} else {
/* If no display specified, default to TCX */
if (graphic_depth != 8 && graphic_depth != 24) {
error_report("Unsupported depth: %d", graphic_depth);
exit(1);
}
if (!(graphic_width == 1024 && graphic_height == 768)) {
error_report("Unsupported resolution: %d x %d",
graphic_width, graphic_height);
exit(1);
}
tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
graphic_width, graphic_height, graphic_depth);
}
}
for (i = num_vsimms; i < MAX_VSIMMS; i++) {
/* vsimm registers probed by OBP */
if (hwdef->vsimm[i].reg_base) {
empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
}
}
if (hwdef->sx_base) {
empty_slot_init(hwdef->sx_base, 0x2000);
}
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
/* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
if (hwdef->apc_base) {
apc_init(hwdef->apc_base, cpu_halt[0]);
}
if (hwdef->fd_base) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
&fdc_tc);
} else {
fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
}
slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
slavio_irq[30], fdc_tc);
if (drive_get_max_bus(IF_SCSI) > 0) {
fprintf(stderr, "qemu: too many SCSI bus\n");
exit(1);
}
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, &esp_reset, &dma_enable);
qdev_connect_gpio_out(espdma, 0, esp_reset);
qdev_connect_gpio_out(espdma, 1, dma_enable);
if (hwdef->cs_base) {
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
slavio_irq[5]);
}
if (hwdef->dbri_base) {
/* ISDN chip with attached CS4215 audio codec */
/* prom space */
empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
/* reg space */
empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
}
if (hwdef->bpp_base) {
/* parallel port */
empty_slot_init(hwdef->bpp_base, 0x20);
}
kernel_size = sun4m_load_kernel(machine->kernel_filename,
machine->initrd_filename,
machine->ram_size);
nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
machine->boot_order, machine->ram_size, kernel_size,
graphic_width, graphic_height, graphic_depth,
hwdef->nvram_machine_id, "Sun4m");
if (hwdef->ecc_base)
ecc_init(hwdef->ecc_base, slavio_irq[28],
hwdef->ecc_version);
fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
machine->kernel_cmdline);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void sun4uv_init(MemoryRegion *address_space_mem,
MachineState *machine,
const struct hwdef *hwdef)
{
SPARCCPU *cpu;
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
SabreState *sabre;
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *iommu, *dev;
FWCfgState *fw_cfg;
NICInfo *nd;
MACAddr macaddr;
bool onboard_nic;
/* init CPUs */
cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
/* IOMMU */
iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU);
qdev_init_nofail(iommu);
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
/* Init sabre (PCI host bridge) */
sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE));
qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu",
&error_abort);
qdev_init_nofail(DEVICE(sabre));
/* Wire up PCI interrupts to CPU */
for (i = 0; i < IVEC_MAX; i++) {
qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
}
pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
/* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
reserved (leaving no slots free after on-board devices) however slots
0-3 are free on busB */
pci_bus->slot_reserved_mask = 0xfffffffc;
pci_busA->slot_reserved_mask = 0xfffffff1;
pci_busB->slot_reserved_mask = 0xfffffff0;
ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
hwdef->console_serial_base);
qdev_init_nofail(DEVICE(ebus));
/* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
memset(&macaddr, 0, sizeof(MACAddr));
onboard_nic = false;
for (i = 0; i < nb_nics; i++) {
nd = &nd_table[i];
if (!nd->model || strcmp(nd->model, "sunhme") == 0) {
if (!onboard_nic) {
pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1),
true, "sunhme");
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
onboard_nic = true;
} else {
pci_dev = pci_create(pci_busB, -1, "sunhme");
}
} else {
pci_dev = pci_create(pci_busB, -1, nd->model);
}
dev = &pci_dev->qdev;
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
}
/* If we don't have an onboard NIC, grab a default MAC address so that
* we have a valid machine id */
if (!onboard_nic) {
qemu_macaddr_default_if_unset(&macaddr);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
qdev_init_nofail(&pci_dev->qdev);
pci_ide_create_devs(pci_dev, hd);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
s = SYS_BUS_DEVICE(nvram);
memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
sysbus_mmio_get_region(s, 0));
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
machine->boot_order,
kernel_addr, kernel_size,
machine->kernel_cmdline,
initrd_addr, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&macaddr);
dev = qdev_create(NULL, TYPE_FW_CFG_IO);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL);
qdev_init_nofail(dev);
memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
&FW_CFG_IO(dev)->comb_iomem);
fw_cfg = FW_CFG(dev);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static void sun4uv_init(MemoryRegion *address_space_mem,
MachineState *machine,
const struct hwdef *hwdef)
{
SPARCCPU *cpu;
Nvram *nvram;
unsigned int i;
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
ISABus *isa_bus;
SysBusDevice *s;
qemu_irq *ivec_irqs, *pbm_irqs;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *fd[MAX_FD];
FWCfgState *fw_cfg;
/* init CPUs */
cpu = cpu_devinit(machine->cpu_model, hwdef);
/* set up devices */
ram_init(0, machine->ram_size);
prom_init(hwdef->prom_addr, bios_name);
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX);
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
&pci_bus3, &pbm_irqs);
pci_vga_init(pci_bus);
// XXX Should be pci_bus3
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
i++;
}
serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS);
parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS);
for(i = 0; i < nb_nics; i++)
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_cmd646_ide_init(pci_bus, hd, 1);
isa_create_simple(isa_bus, "i8042");
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
}
fdctrl_init_isa(isa_bus, fd);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);
s = SYS_BUS_DEVICE(nvram);
memory_region_add_subregion(get_system_io(), 0x2000,
sysbus_mmio_get_region(s, 0));
initrd_size = 0;
initrd_addr = 0;
kernel_size = sun4u_load_kernel(machine->kernel_filename,
machine->initrd_filename,
ram_size, &initrd_size, &initrd_addr,
&kernel_addr, &kernel_entry);
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
machine->boot_order,
kernel_addr, kernel_size,
machine->kernel_cmdline,
initrd_addr, initrd_size,
/* XXX: need an option to load a NVRAM image */
0,
graphic_width, graphic_height, graphic_depth,
(uint8_t *)&nd_table[0].macaddr);
fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (machine->kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
strlen(machine->kernel_cmdline) + 1);
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
}
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
static int
nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next)
{
struct nve0_ram *ram = (void *)pfb->ram;
struct nve0_ramfuc *fuc = &ram->fuc;
int refclk, i;
int ret;
ret = ram_init(fuc, pfb);
if (ret)
return ret;
ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;
/* XXX: this is *not* what nvidia do. on fermi nvidia generally
* select, based on some unknown condition, one of the two possible
* reference frequencies listed in the vbios table for mempll and
* program refpll to that frequency.
*
* so far, i've seen very weird values being chosen by nvidia on
* kepler boards, no idea how/why they're chosen.
*/
refclk = next->freq;
if (ram->mode == 2)
refclk = fuc->mempll.refclk;
/* calculate refpll coefficients */
ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1,
&ram->fN1, &ram->M1, &ram->P1);
fuc->mempll.refclk = ret;
if (ret <= 0) {
nv_error(pfb, "unable to calc refpll\n");
return -EINVAL;
}
/* calculate mempll coefficients, if we're using it */
if (ram->mode == 2) {
/* post-divider doesn't work... the reg takes the values but
* appears to completely ignore it. there *is* a bit at
* bit 28 that appears to divide the clock by 2 if set.
*/
fuc->mempll.min_p = 1;
fuc->mempll.max_p = 2;
ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq,
&ram->N2, NULL, &ram->M2, &ram->P2);
if (ret <= 0) {
nv_error(pfb, "unable to calc mempll\n");
return -EINVAL;
}
}
for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
if (ram_have(fuc, mr[i]))
ram->base.mr[i] = ram_rd32(fuc, mr[i]);
}
ram->base.freq = next->freq;
switch (ram->base.type) {
case NV_MEM_TYPE_DDR3:
ret = nouveau_sddr3_calc(&ram->base);
if (ret == 0)
ret = nve0_ram_calc_sddr3(pfb, next->freq);
break;
case NV_MEM_TYPE_GDDR5:
ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0);
if (ret == 0)
ret = nve0_ram_calc_gddr5(pfb, next->freq);
break;
default:
ret = -ENOSYS;
break;
}
return ret;
}
void petdww_powerup(void)
{
if (petdww_ram) {
ram_init(petdww_ram, PET_DWW_RAM_SIZE);
}
}
static int
nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nva3_ram *ram = (void *)pfb->ram;
struct nva3_ramfuc *fuc = &ram->fuc;
struct nva3_clock_info mclk;
struct nouveau_ram_data *next;
u8 ver, hdr, cnt, len, strap;
u32 data;
u32 r004018, r100760, ctrl;
u32 unk714, unk718, unk71c;
int ret, i;
next = &ram->base.target;
next->freq = freq;
ram->base.next = next;
/* lookup memory config data relevant to the target frequency */
i = 0;
while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len,
&next->bios))) {
if (freq / 1000 >= next->bios.rammap_min &&
freq / 1000 <= next->bios.rammap_max)
break;
}
if (!data || ver != 0x10 || hdr < 0x0e) {
nv_error(pfb, "invalid/missing rammap entry\n");
return -EINVAL;
}
/* locate specific data set for the attached memory */
strap = nvbios_ramcfg_index(nv_subdev(pfb));
if (strap >= cnt) {
nv_error(pfb, "invalid ramcfg strap\n");
return -EINVAL;
}
data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
&ver, &hdr, &next->bios);
if (!data || ver != 0x10 || hdr < 0x0e) {
nv_error(pfb, "invalid/missing ramcfg entry\n");
return -EINVAL;
}
/* lookup memory timings, if bios says they're present */
if (next->bios.ramcfg_timing != 0xff) {
data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
&ver, &hdr, &cnt, &len,
&next->bios);
if (!data || ver != 0x10 || hdr < 0x19) {
nv_error(pfb, "invalid/missing timing entry\n");
return -EINVAL;
}
}
ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
if (ret < 0) {
nv_error(pfb, "failed mclk calculation\n");
return ret;
}
ret = ram_init(fuc, pfb);
if (ret)
return ret;
/* XXX: where the f**k does 750MHz come from? */
if (freq <= 750000) {
r004018 = 0x10000000;
r100760 = 0x22222222;
} else {
r004018 = 0x00000000;
r100760 = 0x00000000;
}
ctrl = ram_rd32(fuc, 0x004000);
if (ctrl & 0x00000008) {
if (mclk.pll) {
ram_mask(fuc, 0x004128, 0x00000101, 0x00000101);
ram_wr32(fuc, 0x004004, mclk.pll);
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef));
ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000);
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010));
ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004));
}
} else {
u32 ssel = 0x00000101;
if (mclk.clk)
ssel |= mclk.clk;
else
ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
}
if (next->bios.ramcfg_10_02_10) {
ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
} else {
ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
}
if (!next->bios.rammap_10_04_02)
ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
ram_wr32(fuc, 0x611200, 0x00003300);
if (!next->bios.ramcfg_10_02_10)
ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
ram_wr32(fuc, 0x1002d4, 0x00000001);
ram_wr32(fuc, 0x1002d0, 0x00000001);
ram_wr32(fuc, 0x1002d0, 0x00000001);
ram_wr32(fuc, 0x100210, 0x00000000);
ram_wr32(fuc, 0x1002dc, 0x00000001);
ram_nsec(fuc, 2000);
ctrl = ram_rd32(fuc, 0x004000);
if (!(ctrl & 0x00000008) && mclk.pll) {
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
ram_wr32(fuc, 0x004018, 0x00001000);
ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001));
ram_wr32(fuc, 0x004004, mclk.pll);
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001));
udelay(64);
ram_wr32(fuc, 0x004018, 0x00005000 | r004018);
udelay(20);
} else
if (!mclk.pll) {
ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk);
ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008));
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000);
ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
}
if (next->bios.rammap_10_04_08) {
ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
next->bios.ramcfg_10_05 << 8 |
next->bios.ramcfg_10_05);
ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
next->bios.ramcfg_10_07);
ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
next->bios.ramcfg_10_03_0f << 16 |
next->bios.ramcfg_10_09_0f |
0x80000000);
ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
} else {
ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000);
ram_mask(fuc, 0x100760, 0x22222222, r100760);
ram_mask(fuc, 0x1007a0, 0x22222222, r100760);
ram_mask(fuc, 0x1007e0, 0x22222222, r100760);
}
if (mclk.pll) {
ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000);
ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008));
}
/*XXX: LEAVE */
ram_wr32(fuc, 0x1002dc, 0x00000000);
ram_wr32(fuc, 0x1002d4, 0x00000001);
ram_wr32(fuc, 0x100210, 0x80000000);
ram_nsec(fuc, 1000);
ram_nsec(fuc, 1000);
ram_mask(fuc, mr[2], 0x00000000, 0x00000000);
ram_nsec(fuc, 1000);
ram_nuke(fuc, mr[0]);
ram_mask(fuc, mr[0], 0x00000000, 0x00000000);
ram_nsec(fuc, 1000);
ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
if (next->bios.ramcfg_10_02_20)
unk714 |= 0xf0000000;
if (!next->bios.ramcfg_10_02_04)
unk714 |= 0x00000010;
ram_wr32(fuc, 0x100714, unk714);
if (next->bios.ramcfg_10_02_01)
unk71c |= 0x00000100;
ram_wr32(fuc, 0x10071c, unk71c);
if (next->bios.ramcfg_10_02_02)
unk718 |= 0x00000100;
ram_wr32(fuc, 0x100718, unk718);
if (next->bios.ramcfg_10_02_10)
ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
ram_mask(fuc, mr[0], 0x100, 0x100);
ram_nsec(fuc, 1000);
ram_mask(fuc, mr[0], 0x100, 0x000);
ram_nsec(fuc, 1000);
ram_nsec(fuc, 2000);
ram_nsec(fuc, 12000);
ram_wr32(fuc, 0x611200, 0x00003330);
if (next->bios.rammap_10_04_02)
ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
if (next->bios.ramcfg_10_02_10) {
ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
} else {
ram_mask(fuc, 0x111104, 0x00000600, 0x00000600);
}
if (mclk.pll) {
ram_mask(fuc, 0x004168, 0x00000001, 0x00000000);
ram_mask(fuc, 0x004168, 0x00000100, 0x00000000);
} else {
ram_mask(fuc, 0x004000, 0x00000001, 0x00000000);
ram_mask(fuc, 0x004128, 0x00000001, 0x00000000);
ram_mask(fuc, 0x004128, 0x00000100, 0x00000000);
}
return 0;
}
int main(int argc, char *argv[])
{
int c;
struct state *state = NULL;
#if TEST_BUILD
struct test_case *test_case;
#endif
prefs_init();
while(1) {
int option_index = 0;
static struct option long_options[] = {
{"cart", required_argument, 0, OPT_CART },
{"force-extreme-disasm", no_argument, 0, OPT_FORCE_EXTREME_DISASM },
{"crop-screen", no_argument, 0, OPT_CROP_SCREEN },
{"loglevels" , required_argument, 0, OPT_LOGLEVELS },
{"audio-device" , required_argument, 0, OPT_AUDIO_DEVICE },
#if TEST_BUILD
{"test-case", required_argument, 0, OPT_TEST_MODE},
#endif
{0, 0, 0, 0 }
};
c = getopt_long(argc, argv, "a:b:c:t:s:hdpyVAMvq", long_options, &option_index);
if(c == -1) break;
switch(c) {
case 'a':
prefs_set("diskimage", optarg);
break;
case 'b':
prefs_set("diskimage2", optarg);
break;
case 'c':
prefs_set("hdimage", optarg);
break;
case 't':
prefs_set("tosimage", optarg);
break;
case 's':
prefs_set("stateimage", optarg);
break;
case OPT_CART:
prefs_set("cartimage", optarg);
break;
case OPT_FORCE_EXTREME_DISASM:
cprint_all = 1;
break;
case OPT_CROP_SCREEN:
crop_screen = 1;
break;
case OPT_LOGLEVELS:
diag_set_module_levels(optarg);
break;
case OPT_AUDIO_DEVICE:
if(!strncmp("list", optarg, 4)) {
audio_device = -1;
} else {
audio_device = atoi(optarg);
}
break;
#if TEST_BUILD
case OPT_TEST_MODE:
test_case_name = xstrdup(optarg);
test_mode = 1;
break;
#endif
case 'd':
debugger = 1;
break;
case 'p':
ppmoutput = 1;
break;
case 'y':
psgoutput = 1;
break;
case 'v':
verbosity++;
break;
case 'q':
verbosity = MAX(1, verbosity-1);
break;
case 'V':
vsync_delay = 1;
break;
case 'A':
play_audio = 1;
break;
case 'M':
monitor_sm124 = 1;
break;
case 'h':
default:
printf("Usage: %s [-AdMpqvVy] [-a diskimage1] [-b diskimage2] [-c hdimage] [-t tosimage] [-s stateimage]\n",
argv[0]);
exit(-1);
break;
}
}
/* Do not crop screen while debugging */
if(debugger) {
crop_screen = 0;
}
if((prefs.diskimage == NULL) && (argv[optind] != NULL))
prefs_set("diskimage", argv[optind]);
SDL_Init(SDL_INIT_VIDEO|SDL_INIT_JOYSTICK|SDL_INIT_AUDIO);
#if TEST_BUILD
if(test_mode) {
test_case = test_init(test_case_name);
if(test_case) {
if(test_case->cartridge_name) {
prefs_set("cartimage", test_case->cartridge_name);
}
if(test_case->floppy_name) {
prefs_set("diskimage", test_case->floppy_name);
}
} else {
printf("DEBUG: Could not load test case %s\n", test_case_name);
exit(-3);
}
}
#endif
/* Must run before hardware module inits */
mmu_init();
/* This must also be run before hardware modules.
It gives a dummy area for some memory regions to not
cause bus errors */
mmu_fallback_init();
/* Actual hardware */
ram_init();
rom_init();
cpu_init();
if(prefs.cartimage) {
cartridge_init(prefs.cartimage);
} else {
cartridge_init(NULL);
}
psg_init();
midi_init();
acia_init();
ikbd_init();
#if INCLUDE_RTC
rtc_init();
#endif
dma_init();
fdc_init();
hdc_init(prefs.hdimage);
mfp_init();
screen_disable(0);
glue_init();
shifter_init();
if(debugger) {
debug_init();
cpu_halt_for_debug();
}
screen_init();
floppy_init(prefs.diskimage, prefs.diskimage2);
if(prefs.stateimage) {
state = state_load(prefs.stateimage);
}
if(state != NULL)
state_restore(state);
memset(&reset, 0, sizeof reset);
reset.sa_sigaction = reset_action;
sigaction(SIGHUP, &reset, NULL);
while(cpu_run(CPU_RUN));
return 0;
}
