void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc) { unsigned int i; if (!rcrtc->crtc.state->active) return; rcar_du_crtc_get(rcrtc); rcar_du_crtc_start(rcrtc); /* Commit the planes state. */ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) { rcar_du_vsp_enable(rcrtc); } else { for (i = 0; i < rcrtc->group->num_planes; ++i) { struct rcar_du_plane *plane = &rcrtc->group->planes[i]; if (plane->plane.state->crtc != &rcrtc->crtc) continue; rcar_du_plane_setup(plane); } } rcar_du_crtc_update_planes(rcrtc); }
static void rcar_du_group_setup(struct rcar_du_group *rgrp) { /* Enable extended features */ rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE); rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G); rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3); rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE); rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5); if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) { rcar_du_group_setup_defr8(rgrp); /* Configure input dot clock routing. We currently hardcode the * configuration to routing DOTCLKINn to DUn. */ rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE | DIDSR_LCDS_DCLKIN(2) | DIDSR_LCDS_DCLKIN(1) | DIDSR_LCDS_DCLKIN(0) | DIDSR_PDCS_CLK(2, 0) | DIDSR_PDCS_CLK(1, 0) | DIDSR_PDCS_CLK(0, 0)); } /* Use DS1PR and DS2PR to configure planes priorities and connects the * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. */ rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); /* Apply planes to CRTCs association. */ mutex_lock(&rgrp->lock); rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) | rgrp->dptsr_planes); mutex_unlock(&rgrp->lock); }
void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc) { if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) rcar_du_vsp_disable(rcrtc); rcar_du_crtc_stop(rcrtc); rcar_du_crtc_put(rcrtc); }
static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); rcar_du_crtc_update_planes(rcrtc); if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) rcar_du_vsp_atomic_flush(rcrtc); }
void rcar_du_crtc_route_output(struct drm_crtc *crtc, enum rcar_du_output output) { struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); struct rcar_du_device *rcdu = rcrtc->group->dev; /* Store the route from the CRTC output to the DU output. The DU will be * configured when starting the CRTC. */ rcrtc->outputs |= BIT(output); /* Store RGB routing to DPAD0 for R8A7790. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) && output == RCAR_DU_OUTPUT_DPAD0) rcdu->dpad0_source = rcrtc->index; }
static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct drm_pending_vblank_event *event = crtc->state->event; struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); struct drm_device *dev = rcrtc->crtc.dev; unsigned long flags; if (event) { WARN_ON(drm_crtc_vblank_get(crtc) != 0); spin_lock_irqsave(&dev->event_lock, flags); rcrtc->event = event; spin_unlock_irqrestore(&dev->event_lock, flags); } if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) rcar_du_vsp_atomic_begin(rcrtc); }
static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc) { struct drm_crtc *crtc = &rcrtc->crtc; if (!rcrtc->started) return; /* Disable all planes and wait for the change to take effect. This is * required as the DSnPR registers are updated on vblank, and no vblank * will occur once the CRTC is stopped. Disabling planes when starting * the CRTC thus wouldn't be enough as it would start scanning out * immediately from old frame buffers until the next vblank. * * This increases the CRTC stop delay, especially when multiple CRTCs * are stopped in one operation as we now wait for one vblank per CRTC. * Whether this can be improved needs to be researched. */ rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); drm_crtc_wait_one_vblank(crtc); /* Disable vertical blanking interrupt reporting. We first need to wait * for page flip completion before stopping the CRTC as userspace * expects page flips to eventually complete. */ rcar_du_crtc_wait_page_flip(rcrtc); drm_crtc_vblank_off(crtc); /* Disable the VSP compositor. */ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) rcar_du_vsp_disable(rcrtc); /* Select switch sync mode. This stops display operation and configures * the HSYNC and VSYNC signals as inputs. */ rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH); rcar_du_group_start_stop(rcrtc->group, false); rcrtc->started = false; }
static int rcar_du_set_dpad0_routing(struct rcar_du_device *rcdu) { int ret; if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS)) return 0; /* RGB output routing to DPAD0 is configured in the DEFR8 register of * the first group. As this function can be called with the DU0 and DU1 * CRTCs disabled, we need to enable the first group clock before * accessing the register. */ ret = clk_prepare_enable(rcdu->crtcs[0].clock); if (ret < 0) return ret; rcar_du_group_setup_defr8(&rcdu->groups[0]); clk_disable_unprepare(rcdu->crtcs[0].clock); return 0; }
static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc) { struct drm_crtc *crtc = &rcrtc->crtc; bool interlaced; if (rcrtc->started) return; /* Set display off and background to black */ rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0)); rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0)); /* Configure display timings and output routing */ rcar_du_crtc_set_display_timing(rcrtc); rcar_du_group_set_routing(rcrtc->group); /* Start with all planes disabled. */ rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0); /* Select master sync mode. This enables display operation in master * sync mode (with the HSYNC and VSYNC signals configured as outputs and * actively driven). */ interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE; rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK | DSYSR_SCM_MASK, (interlaced ? DSYSR_SCM_INT_VIDEO : 0) | DSYSR_TVM_MASTER); rcar_du_group_start_stop(rcrtc->group, true); /* Enable the VSP compositor. */ if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) rcar_du_vsp_enable(rcrtc); /* Turn vertical blanking interrupt reporting back on. */ drm_crtc_vblank_on(crtc); rcrtc->started = true; }
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index) { static const unsigned int mmio_offsets[] = { DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET }; struct rcar_du_device *rcdu = rgrp->dev; struct platform_device *pdev = to_platform_device(rcdu->dev); struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index]; struct drm_crtc *crtc = &rcrtc->crtc; unsigned int irqflags; struct clk *clk; char clk_name[9]; char *name; int irq; int ret; /* Get the CRTC clock and the optional external clock. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { sprintf(clk_name, "du.%u", index); name = clk_name; } else { name = NULL; } rcrtc->clock = devm_clk_get(rcdu->dev, name); if (IS_ERR(rcrtc->clock)) { dev_err(rcdu->dev, "no clock for CRTC %u\n", index); return PTR_ERR(rcrtc->clock); } sprintf(clk_name, "dclkin.%u", index); clk = devm_clk_get(rcdu->dev, clk_name); if (!IS_ERR(clk)) { rcrtc->extclock = clk; } else if (PTR_ERR(rcrtc->clock) == -EPROBE_DEFER) { dev_info(rcdu->dev, "can't get external clock %u\n", index); return -EPROBE_DEFER; } init_waitqueue_head(&rcrtc->flip_wait); rcrtc->group = rgrp; rcrtc->mmio_offset = mmio_offsets[index]; rcrtc->index = index; rcrtc->enabled = false; ret = drm_crtc_init_with_planes(rcdu->ddev, crtc, &rgrp->planes[index % 2].plane, NULL, &crtc_funcs); if (ret < 0) return ret; drm_crtc_helper_add(crtc, &crtc_helper_funcs); /* Start with vertical blanking interrupt reporting disabled. */ drm_crtc_vblank_off(crtc); /* Register the interrupt handler. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { irq = platform_get_irq(pdev, index); irqflags = 0; } else { irq = platform_get_irq(pdev, 0); irqflags = IRQF_SHARED; } if (irq < 0) { dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index); return irq; } ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags, dev_name(rcdu->dev), rcrtc); if (ret < 0) { dev_err(rcdu->dev, "failed to register IRQ for CRTC %u\n", index); return ret; } return 0; }
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index) { static const unsigned int mmio_offsets[] = { DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET }; struct rcar_du_device *rcdu = rgrp->dev; struct platform_device *pdev = to_platform_device(rcdu->dev); struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index]; struct drm_crtc *crtc = &rcrtc->crtc; unsigned int irqflags; char clk_name[5]; char *name; int irq; int ret; /* Get the CRTC clock. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { sprintf(clk_name, "du.%u", index); name = clk_name; } else { name = NULL; } rcrtc->clock = devm_clk_get(rcdu->dev, name); if (IS_ERR(rcrtc->clock)) { dev_err(rcdu->dev, "no clock for CRTC %u\n", index); return PTR_ERR(rcrtc->clock); } rcrtc->group = rgrp; rcrtc->mmio_offset = mmio_offsets[index]; rcrtc->index = index; rcrtc->dpms = DRM_MODE_DPMS_OFF; rcrtc->plane = &rgrp->planes.planes[index % 2]; rcrtc->lvds_ch = -1; rcrtc->plane->crtc = crtc; rcrtc->plane->fb_plane = true; ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs); if (ret < 0) return ret; rcdu->crtcs_connect_id[index] = rcrtc->plane->crtc->base.id; drm_crtc_helper_add(crtc, &crtc_helper_funcs); /* Register the interrupt handler. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) { irq = platform_get_irq(pdev, index); irqflags = 0; } else { irq = platform_get_irq(pdev, 0); irqflags = IRQF_SHARED; } if (irq < 0) { dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index); return ret; } rcdu->ddev->irq_enabled = true; ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags, dev_name(rcdu->dev), rcrtc); if (ret < 0) { dev_err(rcdu->dev, "failed to register IRQ for CRTC %u\n", index); return ret; } return 0; }
static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc) { struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES]; struct rcar_du_device *rcdu = rcrtc->group->dev; unsigned int num_planes = 0; unsigned int dptsr_planes; unsigned int hwplanes = 0; unsigned int prio = 0; unsigned int i; u32 dspr = 0; for (i = 0; i < rcrtc->group->num_planes; ++i) { struct rcar_du_plane *plane = &rcrtc->group->planes[i]; unsigned int j; if (plane->plane.state->crtc != &rcrtc->crtc) continue; /* Insert the plane in the sorted planes array. */ for (j = num_planes++; j > 0; --j) { if (plane_zpos(planes[j-1]) <= plane_zpos(plane)) break; planes[j] = planes[j-1]; } planes[j] = plane; prio += plane_format(plane)->planes * 4; } for (i = 0; i < num_planes; ++i) { struct rcar_du_plane *plane = planes[i]; struct drm_plane_state *state = plane->plane.state; unsigned int index = to_rcar_plane_state(state)->hwindex; prio -= 4; dspr |= (index + 1) << prio; hwplanes |= 1 << index; if (plane_format(plane)->planes == 2) { index = (index + 1) % 8; prio -= 4; dspr |= (index + 1) << prio; hwplanes |= 1 << index; } } /* If VSP+DU integration is enabled the plane assignment is fixed. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) { if (rcdu->info->gen < 3) { dspr = (rcrtc->index % 2) + 1; hwplanes = 1 << (rcrtc->index % 2); } else { dspr = (rcrtc->index % 2) ? 3 : 1; hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0); } } /* Update the planes to display timing and dot clock generator * associations. * * Updating the DPTSR register requires restarting the CRTC group, * resulting in visible flicker. To mitigate the issue only update the * association if needed by enabled planes. Planes being disabled will * keep their current association. */ mutex_lock(&rcrtc->group->lock); dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes : rcrtc->group->dptsr_planes & ~hwplanes; if (dptsr_planes != rcrtc->group->dptsr_planes) { rcar_du_group_write(rcrtc->group, DPTSR, (dptsr_planes << 16) | dptsr_planes); rcrtc->group->dptsr_planes = dptsr_planes; if (rcrtc->group->used_crtcs) rcar_du_group_restart(rcrtc->group); } /* Restart the group if plane sources have changed. */ if (rcrtc->group->need_restart) rcar_du_group_restart(rcrtc->group); mutex_unlock(&rcrtc->group->lock); rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, dspr); }