static void setup_clocks(void) { // Turn on HSI. We'll switch to and run off of this while we're // setting up the main PLL. rcc_turn_on_clk(RCC_CLK_HSI); // Turn off and reset the clock subsystems we'll be using, as well // as the clock security subsystem (CSS). Note that resetting CFGR // to its default value of 0 implies a switch to HSI for SYSCLK. RCC_BASE->CFGR = 0x00000000; rcc_disable_css(); rcc_turn_off_clk(RCC_CLK_PLL); rcc_turn_off_clk(RCC_CLK_HSE); wirish::priv::board_reset_pll(); // Clear clock readiness interrupt flags and turn off clock // readiness interrupts. RCC_BASE->CIR = 0x00000000; // Enable HSE, and wait until it's ready. rcc_turn_on_clk(RCC_CLK_HSE); while (!rcc_is_clk_ready(RCC_CLK_HSE)) ; // Configure AHBx, APBx, etc. prescalers and the main PLL. wirish::priv::board_setup_clock_prescalers(); rcc_configure_pll(&wirish::priv::w_board_pll_cfg); // Enable the PLL, and wait until it's ready. rcc_turn_on_clk(RCC_CLK_PLL); while(!rcc_is_clk_ready(RCC_CLK_PLL)) ; // Finally, switch to the now-ready PLL as the main clock source. rcc_switch_sysclk(RCC_CLKSRC_PLL); }
__deprecated void rcc_clk_init(rcc_sysclk_src sysclk_src, rcc_pllsrc pll_src, rcc_pll_multiplier pll_mul) { /* Assume that we're going to clock the chip off the PLL, fed by * the HSE */ ASSERT(sysclk_src == RCC_CLKSRC_PLL && pll_src == RCC_PLLSRC_HSE); RCC_BASE->CFGR = pll_src | pll_mul | (0x3 << 22); /* Turn on, and wait for, HSE. */ rcc_turn_on_clk(RCC_CLK_HSE); while (!rcc_is_clk_ready(RCC_CLK_HSE)) ; /* Do the same for the main PLL. */ rcc_turn_on_clk(RCC_CLK_PLL); while (!rcc_is_clk_ready(RCC_CLK_PLL)) ; /* Finally, switch over to the PLL. */ rcc_switch_sysclk(RCC_CLKSRC_PLL); }