/*---------------------------------------------------------------------------------------------
* (function: startOdin)
*-------------------------------------------------------------------------------------------*/
void OdinInterface::startOdin()
{
int num_types;
init_options();
//global_args.verilog_file = "/home/kons/Documents/OdinSVN/odin-ii-read-only/ODIN_II/ODIN_II/REGRESSION_TESTS/BENCHMARKS/MICROBENCHMARKS/bm_mod.v";
/* read the FPGA architecture file */
if (global_args.arch_file != NULL)
{
fprintf(stderr, "Reading FPGA Architecture file\n");
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types);
}
if (!global_args.blif_file)
{
/* High level synthesis tool */
do_high_level_synthesis();
}
else
{
read_blif(global_args.blif_file);
}
}
void do_activation_estimation(
int num_types,
t_type_descriptor * type_descriptors)
{
netlist_t *blif_netlist;
netlist_t *net_netlist;
int lut_size;
if ((global_args.activation_blif_file == NULL) || (global_args.activation_netlist_file == NULL) || (global_args.arch_file == NULL))
{
return;
}
lut_size = type_descriptors[2].max_subblock_inputs;
printf("--------------------------------------------------------------------\n");
printf("Activation Estimation Begin\n");
/* read in the blif file */
printf("Reading blif format in for probability densitity estimation\n");
read_blif (global_args.activation_blif_file);
blif_netlist = verilog_netlist;
/* read in the blif file */
/* IO type is known from read_arch library #define EMPTY_TYPE_INDEX 0 #define IO_TYPE_INDEX 1 */
printf("Reading netlist format in for probability densitity estimation\n");
net_netlist = read_netlist (global_args.activation_netlist_file, num_types, type_descriptors, &type_descriptors[1]);
/* do activation estimation */
activity_estimation(NULL, global_args.output_file, lut_size, blif_netlist, net_netlist);
free_netlist(blif_netlist);
free_netlist(net_netlist);
printf("Successful Activation Estimation \n");
printf("--------------------------------------------------------------------\n");
}
int main(int argc, char **argv)
{
int num_types;
printf("--------------------------------------------------------------------\n");
printf("Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)\n");
printf("Email: [email protected] and [email protected] for support issues\n\n");
/* get the command line options */
get_options(argc, argv);
/* read the confirguration file .. get options presets the config values just in case theyr'e not read in with config file */
if (global_args.config_file != NULL)
{
printf("Reading Configuration file\n");
read_config_file(global_args.config_file);
}
/* read the FPGA architecture file */
if (global_args.arch_file != NULL)
{
printf("Reading FPGA Architecture file\n");
#ifdef VPR5
t_clocks ClockDetails = { 0 };
t_power PowerDetails = { 0 };
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types, &ClockDetails, &PowerDetails);
#endif
#ifdef VPR6
XmlReadArch(global_args.arch_file, (boolean)FALSE, &Arch, &type_descriptors, &num_types);
#endif
}
#ifdef VPR5
if (global_args.activation_blif_file != NULL && global_args.activation_netlist_file != NULL)
{
do_activation_estimation(num_types, type_descriptors);
}
else
#endif
{
if (!global_args.blif_file)
{
/* High level synthesis tool */
do_high_level_synthesis();
}
else
{
read_blif(global_args.blif_file);
}
/* Simulate netlist */
do_simulation_of_netlist();
}
#ifdef VPR6
report_mult_distribution();
report_add_distribution();
report_sub_distribution();
deregister_hard_blocks();
#endif
return 0;
}
void try_pack(INP struct s_packer_opts *packer_opts, INP const t_arch * arch, INP t_model *user_models, INP t_model *library_models) {
boolean *is_clock;
int num_models;
t_model *cur_model;
printf("Begin packing of %s \n", packer_opts->blif_file_name);
/* determine number of models in the architecture */
num_models = 0;
cur_model = user_models;
while(cur_model) {
num_models++;
cur_model = cur_model->next;
}
cur_model = library_models;
while(cur_model) {
num_models++;
cur_model = cur_model->next;
}
/* begin parsing blif input file */
read_blif (packer_opts->blif_file_name,
packer_opts->sweep_hanging_nets_and_inputs,
user_models,
library_models);
/* TODO: Do check blif here
eg.
for(i = 0; i < num_logical_blocks; i++) {
if(logical_block[i].model->num_inputs > max_subblock_inputs) {
printf(ERRTAG "logical_block %s of model %s has %d inputs but architecture only supports subblocks up to %d inputs\n",
logical_block[i].name, logical_block[i].model->name, logical_block[i].model->num_inputs, max_subblock_inputs);
exit(1);
}
}
*/
#ifdef DUMP_BLIF_INPUT
echo_input (packer_opts->blif_file_name, "blif_input.echo", library_models);
#endif
absorb_buffer_luts ();
compress_netlist (); /* remove unused inputs */
/* NB: It's important to mark clocks and such *after* compressing the *
* netlist because the vpack_net numbers, etc. may be changed by removing *
* unused inputs . */
is_clock = alloc_and_load_is_clock (packer_opts->global_clocks);
printf("\nAfter removing unused inputs:\n");
printf("Total Blocks: %d. Total Nets: %d. Total inputs %d ouptuts %d\n", num_logical_blocks, num_logical_nets,
num_p_inputs, num_p_outputs);
/* Uncomment line below if you want a dump of compressed netlist. */
/* echo_input (packer_opts->blif_file_name, packer_opts->lut_size, "packed.echo"); */
if (packer_opts->skip_clustering == FALSE) {
do_clustering (arch,
num_models,
packer_opts->global_clocks,
is_clock,
packer_opts->hill_climbing_flag,
packer_opts->output_file,
packer_opts->timing_driven,
packer_opts->cluster_seed_type,
packer_opts->alpha,
packer_opts->beta,
packer_opts->recompute_timing_after,
packer_opts->block_delay,
packer_opts->intra_cluster_net_delay,
packer_opts->inter_cluster_net_delay,
packer_opts->aspect,
packer_opts->allow_unrelated_clustering,
packer_opts->allow_early_exit,
packer_opts->connection_driven,
packer_opts->packer_algorithm,
packer_opts->hack_no_legal_frac_lut,
packer_opts->hack_safe_latch);
}
else {
printf("Skip clustering not supported\n");
exit(1);
}
free (is_clock);
saved_logical_blocks = logical_block;
logical_block = NULL;
num_saved_logical_blocks = num_logical_blocks;
saved_logical_nets = vpack_net;
vpack_net = NULL;
num_saved_logical_nets = num_logical_nets; /* Todo: Use this for error checking */
printf("\nNetlist conversion complete.\n\n");
}
