phys_addr_t __weak mips_cpc_phys_base(void) { u32 cpc_base; if (!mips_cm_present()) return 0; if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) return 0; /* If the CPC is already enabled, leave it so */ cpc_base = read_gcr_cpc_base(); if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; /* Otherwise, give it the default address & enable it */ cpc_base = mips_cpc_default_phys_base(); write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); return cpc_base; }
/** * mips_cpc_phys_base - retrieve the physical base address of the CPC * * This function returns the physical base address of the Cluster Power * Controller memory mapped registers, or 0 if no Cluster Power Controller * is present. */ static phys_addr_t mips_cpc_phys_base(void) { unsigned long cpc_base; if (!mips_cm_present()) return 0; if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX)) return 0; /* If the CPC is already enabled, leave it so */ cpc_base = read_gcr_cpc_base(); if (cpc_base & CM_GCR_CPC_BASE_CPCEN) return cpc_base & CM_GCR_CPC_BASE_CPCBASE; /* Otherwise, use the default address */ cpc_base = mips_cpc_default_phys_base(); if (!cpc_base) return cpc_base; /* Enable the CPC, mapped at the default address */ write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN); return cpc_base; }