int hdmi_pll_enable(void)
{
	u32 status;
	u32 max_reads, timeout_us;

	clk_enable(mdss_dsi_ahb_clk);
	/* Global Enable */
	REG_W(0x81, hdmi_phy_base + HDMI_PHY_GLB_CFG);
	/* Power up power gen */
	REG_W(0x00, hdmi_phy_base + HDMI_PHY_PD_CTRL0);
	udelay(350);

	/* PLL Power-Up */
	REG_W(0x01, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
	udelay(5);
	/* Power up PLL LDO */
	REG_W(0x03, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
	udelay(350);

	/* PLL Power-Up */
	REG_W(0x0F, hdmi_phy_pll_base + HDMI_UNI_PLL_GLB_CFG);
	udelay(350);

	/* poll for PLL ready status */
	max_reads = 20;
	timeout_us = 100;
	if (readl_poll_timeout_noirq((hdmi_phy_pll_base + HDMI_UNI_PLL_STATUS),
		status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
		pr_err("%s: hdmi phy pll status=%x failed to Lock\n",
		       __func__, status);
		hdmi_pll_disable();
		clk_disable(mdss_dsi_ahb_clk);
		return -EINVAL;
	}
	pr_debug("%s: hdmi phy pll is locked\n", __func__);

	udelay(350);
	/* poll for PHY ready status */
	max_reads = 20;
	timeout_us = 100;
	if (readl_poll_timeout_noirq((hdmi_phy_base + HDMI_PHY_STATUS),
		status, ((status & BIT(0)) == 1), max_reads, timeout_us)) {
		pr_err("%s: hdmi phy status=%x failed to Lock\n",
		       __func__, status);
		hdmi_pll_disable();
		clk_disable(mdss_dsi_ahb_clk);
		return -EINVAL;
	}
	pr_debug("%s: hdmi phy is locked\n", __func__);
	clk_disable(mdss_dsi_ahb_clk);

	hdmi_pll_on = 1;

	return 0;
} /* hdmi_pll_enable */
static int hdmi_20nm_pll_lock_status(struct mdss_pll_resources *io)
{
    u32 status;
    int pll_locked = 0;
    int phy_ready = 0;
    int rc;

    rc = mdss_pll_resource_enable(io, true);
    if (rc) {
        pr_err("pll resource can't be enabled\n");
        return rc;
    }

    /* Poll for C_READY and PHY READY */
    pr_debug("%s: Waiting for PHY Ready\n", __func__);

    /* poll for PLL ready status */
    if (!readl_poll_timeout_noirq(
                (io->pll_base + QSERDES_COM_RESET_SM),
                status, ((status & BIT(6)) == 1),
                HDMI_PLL_POLL_MAX_READS,
                HDMI_PLL_POLL_TIMEOUT_US)) {
        pr_debug("%s: C READY\n", __func__);
        pll_locked = 1;
    } else {
        pr_debug("%s: C READY TIMEOUT\n", __func__);
        pll_locked = 0;
    }

    /* poll for PHY ready status */
    if (pll_locked && !readl_poll_timeout_noirq(
                (io->phy_base + HDMI_PHY_STATUS),
                status, ((status & BIT(0)) == 1),
                HDMI_PLL_POLL_MAX_READS,
                HDMI_PLL_POLL_TIMEOUT_US)) {
        pr_debug("%s: PHY READY\n", __func__);
        phy_ready = 1;
    } else {
        pr_debug("%s: PHY READY TIMEOUT\n", __func__);
        phy_ready = 0;
    }
    mdss_pll_resource_enable(io, false);

    return phy_ready;
}
static int dsi_pll_lock_status(void)
{
	u32 status;
	int pll_locked = 0;

	/* poll for PLL ready status */
	if (readl_poll_timeout_noirq((mdss_dsi_base +
			DSI_0_PHY_PLL_UNIPHY_PLL_STATUS),
			status,
			((status & BIT(0)) == 1),
			PLL_POLL_MAX_READS, PLL_POLL_TIMEOUT_US)) {
		pr_debug("%s: DSI PLL status=%x failed to Lock\n",
				__func__, status);
		pll_locked = 0;
	} else {
		pll_locked = 1;
	}

	return pll_locked;
}
示例#4
0
static int mdss_dsi_check_pll_lock(void)
{
	u32 status;

	clk_prepare_enable(mdss_dsi_ahb_clk);
	/* poll for PLL ready status */
	if (readl_poll_timeout_noirq((mdss_dsi_base + 0x02c0),
				status,
				((status & BIT(0)) == 1),
				PLL_POLL_MAX_READS, PLL_POLL_TIMEOUT_US)) {
		pr_err("%s: DSI PLL status=%x failed to Lock\n",
				__func__, status);
		pll_initialized = 0;
	} else {
		pll_initialized = 1;
	}
	clk_disable_unprepare(mdss_dsi_ahb_clk);

	return pll_initialized;
}
static int dsi_pll_lock_status(struct mdss_pll_resources *dsi_pll_res)
{
	u32 status;
	int pll_locked;

	/* poll for PLL ready status */
	if (readl_poll_timeout_noirq((dsi_pll_res->pll_base +
			DSI_PHY_PLL_UNIPHY_PLL_STATUS),
			status,
			((status & BIT(0)) == 1),
			DSI_PLL_POLL_MAX_READS,
			DSI_PLL_POLL_TIMEOUT_US)) {
		pr_debug("DSI PLL status=%x failed to Lock\n", status);
		pll_locked = 0;
	} else {
		pll_locked = 1;
	}

	return pll_locked;
}
static int dsi_pll_enable_seq_8974(void)
{
	int i, rc = 0;
	u32 status, max_reads, timeout_us;

	dsi_pll_software_reset();

	/*
	 * PLL power up sequence.
	 * Add necessary delays recommeded by hardware.
	 */
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
	udelay(1000);
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
	udelay(1000);
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x07);
	udelay(1000);
	DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
	udelay(1000);

	for (i = 0; i < 3; i++) {
		/* DSI Uniphy lock detect setting */
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,
			0x04);
		udelay(100);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_LKDET_CFG2,
			0x05);
		udelay(500);
		/* poll for PLL ready status */
		max_reads = 5;
		timeout_us = 100;
		if (readl_poll_timeout_noirq((mdss_dsi_base +
				DSI_0_PHY_PLL_UNIPHY_PLL_STATUS),
				status,
				((status & 0x01) == 1),
				max_reads, timeout_us)) {
			pr_debug("%s: DSI PLL status=%x failed to Lock\n",
			       __func__, status);
			pr_debug("%s:Trying to power UP PLL again\n",
			       __func__);
		} else {
			break;
		}

		dsi_pll_software_reset();
		/*
		 * PLL power up sequence.
		 * Add necessary delays recommeded by hardware.
		 */
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x1);
		udelay(1000);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
		udelay(1000);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
		udelay(1000);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x5);
		udelay(1000);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x7);
		udelay(1000);
		DSS_REG_W(mdss_dsi_base, DSI_0_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0xf);
		udelay(2000);

	}

	if ((status & 0x01) != 1) {
		pr_debug("%s: DSI PLL status=%x failed to Lock\n",
		       __func__, status);
		rc = -EINVAL;
		goto error;
	}

	pr_debug("%s: DSI PLL Lock success\n", __func__);

error:
	return rc;
}
示例#7
0
static int __mdss_dsi_pll_enable(struct clk *c)
{
	u32 status;
	u32 max_reads, timeout_us;
	int i;

	if (!pll_initialized) {
		if (dsi_pll_rate)
			__mdss_dsi_pll_byte_set_rate(c, dsi_pll_rate);
		else
			pr_err("%s: Calling clk_en before set_rate\n",
						__func__);
	}

	mdss_dsi_uniphy_pll_sw_reset();
	/* PLL power up */
	/* Add HW recommended delay between
	   register writes for the update to propagate */
	REG_W(0x01, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x0f, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);

	for (i = 0; i < 3; i++) {
		mdss_dsi_uniphy_pll_lock_detect_setting();
		/* poll for PLL ready status */
		max_reads = 5;
		timeout_us = 100;
		if (readl_poll_timeout_noirq((mdss_dsi_base + 0x02c0),
				   status,
				   ((status & 0x01) == 1),
					     max_reads, timeout_us)) {
			pr_debug("%s: DSI PLL status=%x failed to Lock\n",
			       __func__, status);
			pr_debug("%s:Trying to power UP PLL again\n",
			       __func__);
		} else
			break;

		mdss_dsi_uniphy_pll_sw_reset();
		udelay(1000);
		/* Add HW recommended delay between
		   register writes for the update to propagate */
		REG_W(0x01, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x0f, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(2000);

	}

	if ((status & 0x01) != 1) {
		pr_err("%s: DSI PLL status=%x failed to Lock\n",
		       __func__, status);
		return -EINVAL;
	}

	pr_debug("%s: **** PLL Lock success\n", __func__);

	return 0;
}