void dump_reg(FILE *outfile, mem_t r) {
reg_id_t id;
for (id = 0; reg_valid(id); id++) {
fprintf(outfile, " %s ", reg_table[id].name);
}
fprintf(outfile, "\n");
for (id = 0; reg_valid(id); id++) {
word_t val = 0;
get_word_val(r, id*4, &val);
fprintf(outfile, " %x", val);
}
fprintf(outfile, "\n");
}
void RegRec::dump(FILE *outfile){
int id;
for (id = 0; reg_valid(id); id++) {
fprintf(outfile, " %s ", reg_table[id].name);
}
fprintf(outfile, "\n");
word_t val;
for (id = 0; reg_valid(id); id++) {
val = 0;
getWord(id*4, &val);
fprintf(outfile, " %x", val);
}
fprintf(outfile, "\n");
}
/* Execute single instruction. Return status. */
stat_t step_state(state_ptr s, FILE *error_file)
{
word_t argA, argB;
byte_t byte0 = 0;
byte_t byte1 = 0;
itype_t hi0;
alu_t lo0;
reg_id_t hi1 = REG_NONE;
reg_id_t lo1 = REG_NONE;
bool_t ok1 = TRUE;
word_t cval = 0;
word_t okc = TRUE;
word_t val, dval;
bool_t need_regids;
bool_t need_imm;
word_t ftpc = s->pc; /* Fall-through PC */
if (!get_byte_val(s->m, ftpc, &byte0)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
ftpc++;
hi0 = HI4(byte0);
lo0 = LO4(byte0);
need_regids =
(hi0 == I_RRMOVL || hi0 == I_ALU || hi0 == I_PUSHL ||
hi0 == I_POPL || hi0 == I_IRMOVL || hi0 == I_RMMOVL ||
hi0 == I_MRMOVL || hi0 == I_IADDL || hi0 == I_ISUBL);
if (need_regids) {
ok1 = get_byte_val(s->m, ftpc, &byte1);
ftpc++;
hi1 = HI4(byte1);
lo1 = LO4(byte1);
}
need_imm =
(hi0 == I_IRMOVL || hi0 == I_RMMOVL || hi0 == I_MRMOVL ||
hi0 == I_JMP || hi0 == I_CALL || hi0 == I_IADDL || hi0 == I_ISUBL);
if (need_imm) {
okc = get_word_val(s->m, ftpc, &cval);
ftpc += 4;
}
switch (hi0) {
case I_NOP:
s->pc = ftpc;
break;
case I_HALT:
return STAT_HLT;
break;
case I_RRMOVL: /* Both unconditional and conditional moves */
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!reg_valid(hi1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, hi1);
return STAT_INS;
}
if (!reg_valid(lo1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, lo1);
return STAT_INS;
}
val = get_reg_val(s->r, hi1);
if (cond_holds(s->cc, lo0))
set_reg_val(s->r, lo1, val);
s->pc = ftpc;
break;
case I_IRMOVL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address",
s->pc);
return STAT_INS;
}
if (!reg_valid(lo1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, lo1);
return STAT_INS;
}
set_reg_val(s->r, lo1, cval);
s->pc = ftpc;
break;
case I_RMMOVL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_INS;
}
if (!reg_valid(hi1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, hi1);
return STAT_INS;
}
if (reg_valid(lo1))
cval += get_reg_val(s->r, lo1);
val = get_reg_val(s->r, hi1);
if (!set_word_val(s->m, cval, val)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid data address 0x%x\n",
s->pc, cval);
return STAT_ADR;
}
s->pc = ftpc;
break;
case I_MRMOVL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction addres\n", s->pc);
return STAT_INS;
}
if (!reg_valid(hi1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, hi1);
return STAT_INS;
}
if (reg_valid(lo1))
cval += get_reg_val(s->r, lo1);
if (!get_word_val(s->m, cval, &val))
return STAT_ADR;
set_reg_val(s->r, hi1, val);
s->pc = ftpc;
break;
case I_ALU:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
argA = get_reg_val(s->r, hi1);
argB = get_reg_val(s->r, lo1);
val = compute_alu(lo0, argA, argB);
set_reg_val(s->r, lo1, val);
s->cc = compute_cc(lo0, argA, argB);
s->pc = ftpc;
break;
case I_JMP:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (cond_holds(s->cc, lo0))
s->pc = cval;
else
s->pc = ftpc;
break;
case I_CALL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
val = get_reg_val(s->r, REG_ESP) - 4;
set_reg_val(s->r, REG_ESP, val);
if (!set_word_val(s->m, val, ftpc)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid stack address 0x%x\n", s->pc, val);
return STAT_ADR;
}
s->pc = cval;
break;
case I_RET:
/* Return Instruction. Pop address from stack */
dval = get_reg_val(s->r, REG_ESP);
if (!get_word_val(s->m, dval, &val)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid stack address 0x%x\n",
s->pc, dval);
return STAT_ADR;
}
set_reg_val(s->r, REG_ESP, dval + 4);
s->pc = val;
break;
case I_PUSHL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!reg_valid(hi1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n", s->pc, hi1);
return STAT_INS;
}
val = get_reg_val(s->r, hi1);
dval = get_reg_val(s->r, REG_ESP) - 4;
set_reg_val(s->r, REG_ESP, dval);
if (!set_word_val(s->m, dval, val)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid stack address 0x%x\n", s->pc, dval);
return STAT_ADR;
}
s->pc = ftpc;
break;
case I_POPL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!reg_valid(hi1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n", s->pc, hi1);
return STAT_INS;
}
dval = get_reg_val(s->r, REG_ESP);
set_reg_val(s->r, REG_ESP, dval+4);
if (!get_word_val(s->m, dval, &val)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid stack address 0x%x\n",
s->pc, dval);
return STAT_ADR;
}
set_reg_val(s->r, hi1, val);
s->pc = ftpc;
break;
case I_LEAVE:
dval = get_reg_val(s->r, REG_EBP);
set_reg_val(s->r, REG_ESP, dval+4);
if (!get_word_val(s->m, dval, &val)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid stack address 0x%x\n",
s->pc, dval);
return STAT_ADR;
}
set_reg_val(s->r, REG_EBP, val);
s->pc = ftpc;
break;
case I_IADDL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address",
s->pc);
return STAT_INS;
}
if (!reg_valid(lo1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, lo1);
return STAT_INS;
}
argB = get_reg_val(s->r, lo1);
val = argB + cval;
set_reg_val(s->r, lo1, val);
s->cc = compute_cc(A_ADD, cval, argB);
s->pc = ftpc;
break;
case I_ISUBL:
if (!ok1) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address\n", s->pc);
return STAT_ADR;
}
if (!okc) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction address",
s->pc);
return STAT_INS;
}
if (!reg_valid(lo1)) {
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid register ID 0x%.1x\n",
s->pc, lo1);
return STAT_INS;
}
argB = get_reg_val(s->r, lo1);
val = argB - cval;
set_reg_val(s->r, lo1, val);
s->cc = compute_cc(A_SUB, cval, argB);
s->pc = ftpc;
break;
default:
if (error_file)
fprintf(error_file,
"PC = 0x%x, Invalid instruction %.2x\n", s->pc, byte0);
return STAT_INS;
}
return STAT_AOK;
}
