static int gs_set_offset( void )
{
int ret;
ret = reg_write(this_gs_data,GS_ADI_REG_OFSX,0x03); /* set OFSX offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSX failed\n");
}
ret = reg_write(this_gs_data,GS_ADI_REG_OFSY,0x03); /* set OFSY offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSY failed\n");
}
ret = reg_write(this_gs_data,GS_ADI_REG_OFSZ,0x0B); /* set OFSZ offset value*/
if (ret < 0) {
printk(KERN_DEBUG "reg_write GS_ADI_REG_OFSZ failed\n");
}
return ret;
}
static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{
int addr;
addr = mv88e6060_port_to_phy_addr(port);
if (addr == -1)
return 0xffff;
return reg_write(ds, addr, regnum, val);
}
void msp430_early_suspend(struct early_suspend *h)
{
char rec_buf;
int ret;
/* mcu enter suspend mode */
rec_buf = priv_data->led_buf[0] & 0xcf;
ret = reg_write(priv_data->client, REG_LED_CTL, rec_buf | SYS_MODE_SUSPEND);
if (ret < 0)
pr_err("mcu: enter suspend mode error!\n");
}
static int gs_resume(struct i2c_client *client)
{
struct gs_data *gs = i2c_get_clientdata(client);
reg_write(gs, GS_ST_REG_CTRL1, GS_ST_CTRL1_PD|
GS_ST_CTRL1_Zen|
GS_ST_CTRL1_Yen|
GS_ST_CTRL1_Xen); /* enable abs int */
reg_write(gs, GS_ST_REG_CTRL3, GS_INTMODE_DATA_READY);/*active mode*/
if (!gs->use_irq)
hrtimer_start(&gs->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
else
enable_irq(client->irq);
return 0;
}
void snd_ak4117_reinit(struct ak4117 *chip)
{
unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
del_timer(&chip->timer);
chip->init = 1;
/* bring the chip to reset state and powerdown state */
reg_write(chip, AK4117_REG_PWRDN, 0);
udelay(200);
/* release reset, but leave powerdown */
reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
udelay(200);
for (reg = 1; reg < 5; reg++)
reg_write(chip, reg, chip->regmap[reg]);
/* release powerdown, everything is initialized now */
reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
chip->init = 0;
chip->timer.expires = 1 + jiffies;
add_timer(&chip->timer);
}
//This function is called on all IRQ interrupts
void timer_inc(void)
{
//increment the number of the timer ticks
++num_timer_tick;
//reset the OSSR[M0]bit
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
osmr_count += CLOCKS_PER_TICK;
//reset the OSCR to 0
reg_write(OSTMR_OSMR_ADDR(0), osmr_count);
}
static void top_write_pin(int pin, TOP_PINMUX_t reg)
{
switch (pin) {
case 4:
reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg);
break;
case 5:
reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg);
break;
case 7:
reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg);
break;
case 8:
reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg);
break;
case 10:
case 11:
case 12:
case 13:
case 14:
case 15:
case 16:
reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS +
((pin - 10) * 4), reg.reg);
break;
default:
reg_write(TOP_BASE + (pin * 4), reg.reg);
break;
}
}
int dcm_armcore(ENUM_ARMCORE_DCM mode)
{
if (mode == ARMCORE_DCM_OFF) {
//swithc to mode 2, and turn wfi/wfe-enable off
reg_write(INFRA_TOPCKGEN_DCMDBC,
and(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0))); //disable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(0x3<<1), (0<<1))); //disable wfi/wfe-en
return 0;
}
if (mode == ARMCORE_DCM_MODE2) {
//switch to mode 2
reg_write(INFRA_TOPCKGEN_DCMDBC,
and(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0))); //disable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(3<<1), (3<<1)));
// OVERRIDE pll mux and clkdiv !!
dcm_armcore_pll_clkdiv(1, (3<<3)|(0)); // armpll, 6/6
}
else if (mode == ARMCORE_DCM_MODE1) {
//switch to mode 1, and mode 2 off
reg_write(INFRA_TOPCKGEN_DCMDBC,
aor(reg_read(INFRA_TOPCKGEN_DCMDBC), ~(1<<0), (1<<0))); //enable mode 1
reg_write(INFRA_TOPCKGEN_DCMCTL,
aor(reg_read(INFRA_TOPCKGEN_DCMCTL), ~(3<<1), (0<<1)));
}
return 0;
}
void irq_handler(void) {
disable_interrupts();
irq_time ++;
dev_update(irq_time);
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
reg_write(OSTMR_OSCR_ADDR, TIMER_CLEAR);
/* Wait for timer to reset */
while(((volatile unsigned)reg_read(INT_ICPR_ADDR) >>INT_OSTMR_0) & 0x1);
dispatch_save();
}
/* in this function, we configure the OS timer register */
void timer_init(void)
{
//size_t num_clock;
//calculate the clocks for a time unit: 10ms for now
//Will change to the following line if set to 10ms
//num_clock = OSTMR_FREQ/OS_TICKS_PER_SEC;
//num_clock = OSTMR_FREQ/(S_TO_MS/MS_PER_TICK);
osmr_count = CLOCKS_PER_TICK;
//init OSCR to 0
reg_write(OSTMR_OSCR_ADDR, 0);
//init OSMR0 to num_clock
reg_write(OSTMR_OSMR_ADDR(0), osmr_count);
/*
* set OIER last bit 1 to enbale match between OSCR
* and OSMR0 to assert OSSR[M0]
*/
reg_set(OSTMR_OIER_ADDR, OSTMR_OIER_E0);
}
/*
* platform operation relate functions
*/
static int aac_sensor_probe(struct i2c_client *client,const struct i2c_device_id *idp)
{
struct sensor_device *dev;
u8 val;
dev=&sensor_priv;
/* initualize wait queue */
init_completion(&dev->data_comp);
INIT_DELAYED_WORK(&dev->data_work,aac_sensor_work);
if(sensor_interrupt_init()){
sensor_error("Fail to config gpio port\n");
return -1;
}
if(request_irq(IRQ_EINT5, aac_sensor_irq,IRQF_DISABLED,"aac_sensor",dev)){
sensor_error("Fail to request gpio interrupt\n");
return -1;
}
sensor_interrupt_disable();
sensor_interrupt_clear();
reg_write(client,MMA_MODE,0); //Make 7660 enter standby mode to set registers
reg_write(client,MMA_SPCNT,0xff);
reg_write(client,MMA_INTSU,MMA_INT_FB|MMA_INT_PL/*|MMA_INT_PD*/);
val=0;
SET_BITS(val,MMA_SR_AMSR,AMSR_RATE_128);
SET_BITS(val,MMA_SR_AWSR,AWSR_RATE_32);
SET_BITS(val,MMA_SR_FILT,FILT_DISABLE);
reg_write(client,MMA_SR,val);
val=0;
SET_BITS(val,MMA_PDET_PDTH,2);
SET_BITS(val,MMA_PDET_XDA,1);
SET_BITS(val,MMA_PDET_YDA,1);
SET_BITS(val,MMA_PDET_ZDA,1);
reg_write(client,MMA_PDET,val);
reg_write(client,MMA_PD,0x1f);
reg_write(client,MMA_MODE,
MMA_MODE_MODE|MMA_MODE_AWE| //active
MMA_MODE_ASE/*|MMA_MODE_SCPS*/| //auto wake/suspend
MMA_MODE_IPP); //int active low
sensor_priv.client=client;
//i2c_set_clientdata(client, nas_priv);
return 0;
}
static int ak881x_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (reg->reg > 0x26)
return -EINVAL;
if (reg_write(client, reg->reg, reg->val) < 0)
return -EIO;
return 0;
}
/*
* mv_xor_ctrl_set - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
* NOTE:
* This function does not modify the Operation_mode field of control register.
*/
int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
{
u32 old_value;
/* update the XOR Engine [0..1] Configuration Registers (XEx_c_r) */
old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) &
XEXCR_OPERATION_MODE_MASK;
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
xor_ctrl |= old_value;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
return MV_OK;
}
/*
* mv_xor_ctrl_set - Set XOR channel control registers
*
* DESCRIPTION:
*
* INPUT:
*
* OUTPUT:
* None.
*
* RETURN:
* MV_BAD_PARAM if parameters to function invalid, MV_OK otherwise.
* NOTE:
* This function does not modify the OperationMode field of control register.
*
*/
static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl)
{
u32 val;
/* Update the XOR Engine [0..1] Configuration Registers (XExCR) */
val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)))
& XEXCR_OPERATION_MODE_MASK;
xor_ctrl &= ~XEXCR_OPERATION_MODE_MASK;
xor_ctrl |= val;
reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl);
return MV_OK;
}
static void hw_r5_enable_clock(struct zynqmp_r5_rproc_pdata *pdata)
{
u32 tmp;
pr_debug("%s: mode: %d\n", __func__, pdata->rpu_mode);
tmp = reg_read(pdata->crl_apb_base, CPU_R5_CTRL_OFFSET);
if (!(tmp & RPU_CLKACT_MASK)) {
tmp |= RPU_CLKACT_MASK;
reg_write(pdata->crl_apb_base, CPU_R5_CTRL_OFFSET, tmp);
/* Give some delay for clock to propogate */
udelay(500);
}
}
/*
* TODO: Update HW ipi operation when the driver is ready
*/
static irqreturn_t hw_clear_ipi(struct zynqmp_r5_rproc_pdata *pdata)
{
u32 ipi_reg = 0;
pr_debug("%s: irq issuer %08x clear IPI\n", __func__,
pdata->ipi_dest_mask);
ipi_reg = reg_read(pdata->ipi_base, ISR_OFFSET);
if (ipi_reg & pdata->ipi_dest_mask) {
reg_write(pdata->ipi_base, ISR_OFFSET, pdata->ipi_dest_mask);
return IRQ_HANDLED;
}
return IRQ_NONE;
}
static int gs_st_open(struct inode *inode, struct file *file)
{
reg_read(this_gs_data, GS_ST_REG_STATUS ); /* read status */
reg_write(this_gs_data, GS_ST_REG_CTRL1, GS_ST_CTRL1_PD|
GS_ST_CTRL1_Zen|
GS_ST_CTRL1_Yen|
GS_ST_CTRL1_Xen);
reg_write(this_gs_data, GS_ST_REG_CTRL3, GS_INTMODE_DATA_READY);
reg_read(this_gs_data, GS_ST_REG_OUT_X ); /* read X */
reg_read(this_gs_data, GS_ST_REG_OUT_Y ); /* read Y */
reg_read(this_gs_data, GS_ST_REG_OUT_Z ); /* read Z*/
if (this_gs_data->use_irq)
enable_irq(this_gs_data->client->irq);
else
hrtimer_start(&this_gs_data->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
return nonseekable_open(inode, file);
}
static int get_phy_reg(struct ti_lynx *lynx, int addr)
{
int retval;
int i = 0;
unsigned long flags;
if (addr > 15) {
PRINT(KERN_ERR, lynx->id,
"%s: PHY register address %d out of range",
__FUNCTION__, addr);
return -1;
}
spin_lock_irqsave(&lynx->phy_reg_lock, flags);
reg_write(lynx, LINK_PHY, LINK_PHY_READ | LINK_PHY_ADDR(addr));
do {
retval = reg_read(lynx, LINK_PHY);
if (i > 10000) {
PRINT(KERN_ERR, lynx->id, "%s: runaway loop, aborting",
__FUNCTION__);
retval = -1;
break;
}
i++;
} while ((retval & 0xf00) != LINK_PHY_RADDR(addr));
reg_write(lynx, LINK_INT_STATUS, LINK_INT_PHY_REG_RCVD);
spin_unlock_irqrestore(&lynx->phy_reg_lock, flags);
if (retval != -1) {
return retval & 0xff;
} else {
return -1;
}
}
static int mxci2c_hs_read(mxc_i2c_hs *i2c_hs, int repeat_start,
struct i2c_msg *msg)
{
int ret;
if (msg->len > HIRDCR_MAX_COUNT) {
printk(KERN_ERR "%s: error: msg too long, max longth 256\n",
__func__);
return -1;
}
ret = 0;
i2c_hs->msg = msg;
i2c_hs->index = 0;
/*set address */
reg_write(i2c_hs, HIMADR, HIMADR_LSB_ADR(msg->addr));
/*receive mode */
reg_clear_mask(i2c_hs, HICR, HICR_MTX);
reg_clear_mask(i2c_hs, HICR, HICR_HIIEN);
/*FIFO*/ reg_set_mask(i2c_hs, HIRFR, HIRFR_RFEN | HIRFR_RFWM(7));
reg_set_mask(i2c_hs, HIRFR, HIRFR_RFLSH);
/*TDCR*/
reg_write(i2c_hs, HIRDCR, HIRDCR_RDC_EN | HIRDCR_RDC(msg->len));
mxci2c_hs_start(i2c_hs, repeat_start, msg->addr);
ret = mxci2c_wait_readfifo(i2c_hs);
if (ret < 0)
return ret;
else
return msg->len;
}
int top_set_pin(int pin, int func)
{
TOP_PINMUX_t reg;
/* check global range */
if ((pin < 0) || (pin > 158))
return -1; /* pin number or function out of valid range */
reg.reg = reg_read(TOP_BASE + (pin * 4));
reg.Bits.funsel = func;
reg_write(TOP_BASE + (pin * 4), reg.reg);
return 0;
}
static void hw_r5_reset(struct zynqmp_r5_rproc_pdata *pdata,
bool do_reset)
{
u32 tmp;
pr_debug("%s: R5 ID: %d, reset %d\n", __func__, pdata->rpu_id,
do_reset);
tmp = reg_read(pdata->crl_apb_base, RST_LPD_TOP_OFFSET);
if (do_reset)
tmp |= (RPU0_RESET_BIT << pdata->rpu_id);
else
tmp &= ~(RPU0_RESET_BIT << pdata->rpu_id);
reg_write(pdata->crl_apb_base, RST_LPD_TOP_OFFSET, tmp);
}
static irqreturn_t unicam_isr(int irq, void *dev_id)
{
struct unicam *dev;
unsigned int rx_status, image_intr;
dev = dev_id;
rx_status = reg_read(unicam_base, CAM_STA_OFFSET);
image_intr = reg_read(unicam_base, CAM_ISTA_OFFSET);
/* enable access */
reg_write(unicam_base, CAM_ISTA_OFFSET, image_intr);
reg_write(unicam_base, CAM_STA_OFFSET, rx_status);
if (dev->irq_start == 1) {
if (dev->irq_pending == 0) {
dev->unicam_isr_reg_status.rx_status = rx_status;
dev->unicam_isr_reg_status.image_intr = image_intr;
complete(&dev->irq_sem);
}
dev->irq_pending++;
}
return IRQ_RETVAL(1);
}
int dcm_topckg_dbc(int on, int cnt)
{
int value;
cnt &= 0x7f;
on = (on != 0) ? 1 : 0;
value = (cnt<<8) | (cnt<<24) | (on<<15) | (on<<31);
reg_write(TOPCKG_DCM_CFG, aor(reg_read(TOPCKG_DCM_CFG),
~( (0xff<<8) | (0xff<<24)),
value));
return 0;
}
static int gs_resume(struct i2c_client *client)
{
struct gs_data *gs = i2c_get_clientdata(client);
/*BK4D00238, add accelerometer code, dingxifeng KF14049, 2009-5-9 begin */
reg_write(gs,GS_ADI_REG_POWER_CTL,0x08);/* measure mode */
/*BK4D00238, add accelerometer code, dingxifeng KF14049, 2009-5-9 end */
if (gs->use_irq)
{
/*BK4D00238, add accelerometer code, dingxifeng KF14049, 2009-5-9 begin */
reg_write(gs,GS_ADI_REG_INT_ENABLE,0xe0);/* enable int */
/*BK4D00238, add accelerometer code, dingxifeng KF14049, 2009-5-9 end */
enable_irq(client->irq);
}
if (!gs->use_irq)
hrtimer_start(&gs->timer, ktime_set(1, 0), HRTIMER_MODE_REL);
return 0;
}
static int gs_st_release(struct inode *inode, struct file *file)
{
reg_write(this_gs_data, GS_ST_REG_CTRL1, 0x00);
if (this_gs_data->use_irq)
disable_irq(this_gs_data->client->irq);
else
hrtimer_cancel(&this_gs_data->timer);
accel_delay = GS_ST_TIMRER;
return 0;
}
void irq_handler(void){
if((reg_read(INT_ICPR_ADDR) & (INT_ICCR_DIM << INT_OSTMR_0)) && (reg_read(OSTMR_OSSR_ADDR) & OSTMR_OSSR_M0)){
kernel_time += irq_elapse_time;
reg_write(OSTMR_OSMR_ADDR(0), reg_read(OSTMR_OSCR_ADDR) + irq_elapse_count);
reg_set(OSTMR_OSSR_ADDR, OSTMR_OSSR_M0);
}
return ;
}
static int event_double_check_thd(void *ptr)
{
char event = *(char *)ptr;
char rec_buf;
kfree(ptr);
if (!priv_data->is_mcu_ready) {
pr_err("%s:mcu is not ready!!\n", __func__);
return 0;
}
pr_info("%s: check event:%d\n", __func__, event);
if (event == INT_BATLOSS_EVENT) {
pr_info("double check battery lost event!\n");
if (priv_data->get_charger_type &&
(priv_data->get_charger_type() == CHARGER_TYPE_NONE)) {
pr_info("No charger. Fake battery lost event?\n");
return 0;
}
/* reg 0xa, bit3-> battery detect, 0 means battery lost */
rw_gauge_reg(GAUGE_READ, 0x0A, 0x00, &rec_buf);
if (rec_buf & 0x8) {
pr_info("fake battery lost event?\n");
} else {
if (priv_data->battery_isr_hander) {
reg_write(priv_data->client, REG_KEYPAD_PWM, 0);
reg_write(priv_data->client, REG_CAHRGER_STATUS, 0);
reg_write(priv_data->client, REG_LED_CTL, 0);
priv_data->battery_isr_hander(FLAG_BATT_LOST);
} else
pr_err("Battery lost but no handler registered.\n");
}
}
return 0;
}
static void reset_l2_reg()
{
reg_write(IO_ADDRESS(L2_INT_COUNTER2), UNSIGNED_INT_MAX);
reg_write(IO_ADDRESS(L2_INT_COUNTER3), UNSIGNED_INT_MAX);
reg_write(IO_ADDRESS(L2_INT_COUNTER4), UNSIGNED_INT_MAX);
reg_write(IO_ADDRESS(L2_INT_COUNTER5), UNSIGNED_INT_MAX);
reg_write(IO_ADDRESS(L2_INT_COUNTER6), UNSIGNED_INT_MAX);
reg_write(IO_ADDRESS(L2_INT_COUNTER7), UNSIGNED_INT_MAX);
}
static int snd_ak4117_rx_put(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_value *ucontrol)
{
struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
int change;
u8 old_val;
spin_lock_irq(&chip->lock);
old_val = chip->regmap[AK4117_REG_IO];
change = !!ucontrol->value.integer.value[0] != ((old_val & AK4117_IPS) ? 1 : 0);
if (change)
reg_write(chip, AK4117_REG_IO, (old_val & ~AK4117_IPS) | (ucontrol->value.integer.value[0] ? AK4117_IPS : 0));
spin_unlock_irq(&chip->lock);
return change;
}
static int stm32_iwdg_start(struct watchdog_device *wdd)
{
struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
u32 val = FLAG_PVU | FLAG_RVU;
u32 reload;
int ret;
dev_dbg(wdd->parent, "%s\n", __func__);
/* prescaler fixed to 256 */
reload = clamp_t(unsigned int, ((wdd->timeout * wdt->rate) / 256) - 1,
RLR_MIN, RLR_MAX);
/* enable write access */
reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
/* set prescaler & reload registers */
reg_write(wdt->regs, IWDG_PR, PR_256); /* prescaler fix to 256 */
reg_write(wdt->regs, IWDG_RLR, reload);
reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
/* wait for the registers to be updated (max 100ms) */
ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, val,
!(val & (FLAG_PVU | FLAG_RVU)),
SLEEP_US, TIMEOUT_US);
if (ret) {
dev_err(wdd->parent,
"Fail to set prescaler or reload registers\n");
return ret;
}
/* reload watchdog */
reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
return 0;
}
