IMG_VOID RgxSunxiInit(IMG_VOID)
{
ParseFexPara();
rgx_regulator = regulator_get(NULL, "axp22_dcdc2");
if (IS_ERR(rgx_regulator)) {
printk(KERN_ERR "Failed to get rgx regulator \n");
rgx_regulator = NULL;
}
gpu_core_clk = clk_get(NULL, GPUCORE_CLK);
gpu_mem_clk = clk_get(NULL, GPUMEM_CLK);
gpu_axi_clk = clk_get(NULL, GPUAXI_CLK);
gpu_pll_clk = clk_get(NULL, PLL9_CLK);
SetGpuVol(min_vf_level_val);
SetClkVal("pll", vf_table[min_vf_level_val][1]);
SetClkVal("core", vf_table[min_vf_level_val][1]);
SetClkVal("mem", vf_table[min_vf_level_val][1]);
SetClkVal("axi", AXI_CLK_FREQ);
RgxResume();
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&rgx_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
printk(KERN_INFO "Sunxi init successfully\n");
}
IMG_VOID RgxSunxiInit(IMG_VOID)
{
ParseFexPara();
rgx_regulator = regulator_get(NULL, regulator_id);
if (IS_ERR(rgx_regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get rgx regulator!"));
rgx_regulator = NULL;
return;
}
gpu_core_clk = clk_get(NULL, GPUCORE_CLK);
gpu_mem_clk = clk_get(NULL, GPUMEM_CLK);
gpu_axi_clk = clk_get(NULL, GPUAXI_CLK);
gpu_pll_clk = clk_get(NULL, PLL9_CLK);
gpu_ctrl_clk = clk_get(NULL, GPU_CTRL);
SetGpuVol(min_vf_level_val);
SetClkVal("pll", vf_table[min_vf_level_val][1]);
SetClkVal("core", vf_table[min_vf_level_val][1]);
SetClkVal("mem", vf_table[min_vf_level_val][1]);
SetClkVal("axi", AXI_CLK_FREQ);
RgxResume();
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&rgx_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
}
/*
***************************************************************
@Function :sunxi_mali_platform_device_register
@Description :Register mali platform device
@Input :None
@Return :0 or error code
***************************************************************
*/
int sunxi_mali_platform_device_register(void)
{
int err;
unsigned long mem_size = 0;
struct __fb_addr_para fb_addr_para={0};
sunxi_get_fb_addr_para(&fb_addr_para);
err = platform_device_add_resources(&mali_gpu_device, mali_gpu_resources, sizeof(mali_gpu_resources) / sizeof(mali_gpu_resources[0]));
if (0 == err){
mali_gpu_data.fb_start = fb_addr_para.fb_paddr;
mali_gpu_data.fb_size = fb_addr_para.fb_size;
mem_size = (totalram_pages * PAGE_SIZE )/1024; /* KB */
if(mem_size > 512*1024)
{
mali_gpu_data.shared_mem_size = 1024*1024*1024;
}
else
{
mali_gpu_data.shared_mem_size = 512*1024*1024;
}
err = platform_device_add_data(&mali_gpu_device, &mali_gpu_data, sizeof(mali_gpu_data));
if(0 == err)
{
err = platform_device_register(&mali_gpu_device);
if (0 == err){
if(_MALI_OSK_ERR_OK != mali_platform_init())
{
return _MALI_OSK_ERR_FAULT;
}
#ifdef CONFIG_PM_RUNTIME
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
pm_runtime_set_autosuspend_delay(&(mali_gpu_device.dev), 1000);
pm_runtime_use_autosuspend(&(mali_gpu_device.dev));
#endif
pm_runtime_enable(&(mali_gpu_device.dev));
#endif /* CONFIG_PM_RUNTIME */
/* print mali gpu information */
printk(KERN_INFO "=========================================================\n");
printk(KERN_INFO " Mali GPU Information \n");
printk(KERN_INFO "voltage : %d mV\n", regulator_get_voltage(mali_regulator)/1000);
printk(KERN_INFO "initial frequency : %ld MHz\n", clk_get_rate(h_mali_clk)/(1000*1000));
printk(KERN_INFO "frame buffer address: 0x%lx - 0x%lx\n", mali_gpu_data.fb_start, mali_gpu_data.fb_start + mali_gpu_data.shared_mem_size);
printk(KERN_INFO "frame buffer size : %ld MB\n", mali_gpu_data.shared_mem_size/(1024*1024));
printk(KERN_INFO "=========================================================\n");
return 0;
}
}
platform_device_unregister(&mali_gpu_device);
}
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&mali_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
return err;
}
/*!
******************************************************************************
@Function EnableSystemClocks
@Description Setup up the clocks for the graphics device to work.
@Return PVRSRV_ERROR
******************************************************************************/
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
if (!psSysSpecData->bSysClocksOneTimeInit)
{
if(NULL != private_data.regulator_id)
{
private_data.regulator = regulator_get(NULL,private_data.regulator_id);
if (IS_ERR(private_data.regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu regulator!"));
}
}
if(regulator_enable(private_data.regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to enable gpu external power!"));
}
#ifdef CONFIG_CPU_BUDGET_THERMAL
private_data.tempctrl_data.count = sizeof(tf_table)/sizeof(tf_table[0]);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
ParseFex();
private_data.max_freq = vf_data.extreme.freq;
GetGpuClk();
SetGpuClkParent();
SetGpuVol(vf_data.normal.vol);
SetClkVal(vf_data.normal.freq);
mutex_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
mutex_init(&private_data.dvfs_lock);
sysfs_create_group(&gpsPVRLDMDev->dev.kobj, &gpu_attribute_group);
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&gpu_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
}
EnableGpuPower();
/* Delay for gpu power stability */
mdelay(2);
/* Set gpu power off gating invalid */
SetBit(private_data.poweroff_gate.bit, 0, private_data.poweroff_gate.addr);
DeAssertGpuResetSignal();
return PVRSRV_OK;
}
/*!
******************************************************************************
@Function EnableSystemClocks
@Description Setup up the clocks for the graphics device to work.
@Return PVRSRV_ERROR
******************************************************************************/
PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (!psSysSpecData->bSysClocksOneTimeInit)
{
sgx_regulator = regulator_get(NULL,"vdd-gpu");
if (IS_ERR(sgx_regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get sgx regulator!"));
}
ParseSysconfigFex();
/* Set up PLL and clock parents */
gpu_pll_clk = clk_get(NULL,PLL_GPU_CLK);
if (!gpu_pll_clk || IS_ERR(gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu pll handle!"));
}
gpu_core_clk = clk_get(NULL, GPUCORE_CLK);
if (!gpu_core_clk || IS_ERR(gpu_core_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu core clock handle!"));
}
gpu_mem_clk = clk_get(NULL, GPUMEM_CLK);
if (!gpu_mem_clk || IS_ERR(gpu_mem_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu mem clock handle!"));
}
gpu_hyd_clk = clk_get(NULL, GPUHYD_CLK);
if (!gpu_hyd_clk || IS_ERR(gpu_hyd_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to get gpu hyd clock handle!"));
}
if (clk_set_parent(gpu_core_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu core clock!"));
}
if (clk_set_parent(gpu_mem_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu mem clock!"));
}
if (clk_set_parent(gpu_hyd_clk, gpu_pll_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to set the parent of gpu hyd clock!"));
}
/* set the frequency of gpu pll */
SetGpuFreq(dvfs_level);
mutex_init(&psSysSpecData->sPowerLock);
psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
mutex_init(&dvfs_lock);
#ifdef CONFIG_CPU_BUDGET_THERMAL
register_budget_cooling_notifier(&sgx_throttle_notifier);
#endif /* CONFIG_CPU_BUDGET_THERMAL */
sysfs_create_group(&gpsPVRLDMDev->dev.kobj, &gpu_attribute_group);
}
/* enable gpu power */
if (regulator_enable(sgx_regulator))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to enable gpu power!"));
}
/* delay for gpu power stability */
mdelay(2);
/* set gpu power off gating invalid */
sunxi_smc_writel(0, SUNXI_R_PRCM_VBASE + 0x118);
if(sunxi_periph_reset_deassert(gpu_hyd_clk))
{
PVR_DPF((PVR_DBG_ERROR, "Failed to release gpu reset!"));
}
return PVRSRV_OK;
}
