static int max98505_probe(struct snd_soc_codec *codec) { struct max98505_priv *max98505 = snd_soc_codec_get_drvdata(codec); struct max98505_pdata *pdata = max98505->pdata; struct max98505_cdata *cdata; int ret = 0; int reg = 0; dev_info(codec->dev, "build number %s\n", MAX98505_REVISION); max98505->codec = codec; codec->control_data = max98505->regmap; ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); if (ret != 0) { dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); return ret; } max98505->sysclk = pdata->sysclk; max98505->volume = pdata->spk_vol; cdata = &max98505->dai[0]; cdata->rate = (unsigned)-1; cdata->fmt = (unsigned)-1; reg = 0; ret = regmap_read(max98505->regmap, MAX98505_R0FF_VERSION, ®); if ((ret < 0) || ((reg != MAX98505_VERSION) && (reg != MAX98505_VERSION1) && (reg != MAX98505_VERSION2) && (reg != MAX98505_VERSION3))) { dev_err(codec->dev, "device initialization error (%d 0x%02X)\n", ret, reg); goto err_version; } msg_maxim("device version 0x%02x", reg); regmap_write(max98505->regmap, MAX98505_R038_GLOBAL_ENABLE, 0x00); /* It's not the default but we need to set DAI_DLY */ regmap_write(max98505->regmap, MAX98505_R020_FORMAT, MAX98505_DAI_DLY_MASK); regmap_write(max98505->regmap, MAX98505_R021_TDM_SLOT_SELECT, 0xC8); regmap_write(max98505->regmap, MAX98505_R027_DOUT_HIZ_CFG1, 0xFF); regmap_write(max98505->regmap, MAX98505_R028_DOUT_HIZ_CFG2, 0xFF); regmap_write(max98505->regmap, MAX98505_R029_DOUT_HIZ_CFG3, 0xFF); regmap_write(max98505->regmap, MAX98505_R02A_DOUT_HIZ_CFG4, 0xF0); regmap_write(max98505->regmap, MAX98505_R02C_FILTERS, 0xD9); regmap_write(max98505->regmap, MAX98505_R034_ALC_CONFIGURATION, 0x12); /* Set boost output to maximum */ regmap_write(max98505->regmap, MAX98505_R037_CONFIGURATION, 0x00); /* Disable ALC muting */ regmap_write(max98505->regmap, MAX98505_R03A_BOOST_LIMITER, 0xF8); regmap_update_bits(max98505->regmap, MAX98505_R02D_GAIN, MAX98505_DAC_IN_SEL_MASK, MAX98505_DAC_IN_SEL_DIV2_SUMMED_DAI); /* Enable ADC */ regmap_update_bits(max98505->regmap, MAX98505_R036_BLOCK_ENABLE, MAX98505_ADC_VIMON_EN_MASK, MAX98505_ADC_VIMON_EN_MASK); pdata->vstep.adc_status = 1; max98505_set_slave(max98505); max98505_handle_pdata(codec); max98505_add_widgets(codec); #if defined(USE_DSM_LOG) || defined(USE_DSM_UPDATE_CAL) if (!g_class) g_class = class_create(THIS_MODULE, class_name_log); max98505->dev_log_class = g_class; if (max98505->dev_log_class) { max98505->dev_log = device_create(max98505->dev_log_class, NULL, 1, NULL, "max98505"); if (IS_ERR(max98505->dev_log)) { ret = sysfs_create_group(&codec->dev->kobj, &max98505_attribute_group); if (ret) msg_maxim( "failed to create sysfs group [%d]", ret); } else { ret = sysfs_create_group(&max98505->dev_log->kobj, &max98505_attribute_group); if (ret) msg_maxim( "failed to create sysfs group [%d]", ret); } } msg_maxim("g_class=%p %p", g_class, max98505->dev_log_class); #endif /* USE_DSM_LOG || USE_DSM_UPDATE_CAL */ err_version: msg_maxim("exit %d", ret); return ret; }
int sec_reg_write(struct sec_pmic_dev *sec_pmic, u8 reg, u8 value) { return regmap_write(sec_pmic->regmap_pmic, reg, value); }
int arizona_irq_init(struct arizona *arizona) { int flags = IRQF_ONESHOT; int ret, i; struct regmap_irq_chip *aod, *irq; bool ctrlif_error = true; int irq_base; switch (arizona->type) { #ifdef CONFIG_MFD_WM5102 case WM5102: aod = &wm5102_aod; irq = &wm5102_irq; ctrlif_error = false; break; #endif #ifdef CONFIG_MFD_WM5110 case WM5110: aod = &wm5110_aod; irq = &wm5110_irq; ctrlif_error = false; break; #endif default: BUG_ON("Unknown Arizona class device" == NULL); return -EINVAL; } /* Disable all wake sources by default */ regmap_write(arizona->regmap, ARIZONA_WAKE_CONTROL, 0); if (arizona->pdata.irq_active_high) { ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ_CTRL_1, ARIZONA_IRQ_POL, 0); if (ret != 0) { dev_err(arizona->dev, "Couldn't set IRQ polarity: %d\n", ret); goto err; } flags |= IRQF_TRIGGER_HIGH; } else { flags |= IRQF_TRIGGER_LOW; } /* set virtual IRQs */ if (arizona->pdata.irq_base > 0) { arizona->virq[0] = arizona->pdata.irq_base; arizona->virq[1] = arizona->pdata.irq_base + 1; irq_base = arizona->pdata.irq_base + 2; } else { dev_err(arizona->dev, "No irq_base specified\n"); return -EINVAL; } for (i = 0; i < ARRAY_SIZE(arizona->virq); i++) { irq_set_chip_and_handler(arizona->virq[i], &arizona_irq_chip, handle_edge_irq); irq_set_nested_thread(arizona->virq[i], 1); /* ARM needs us to explicitly flag the IRQ as valid * and will set them noprobe when we do so. */ #ifdef CONFIG_ARM set_irq_flags(arizona->virq[i], IRQF_VALID); #else irq_set_noprobe(arizona->virq[i]); #endif } ret = regmap_add_irq_chip(arizona->regmap, arizona->virq[0], IRQF_ONESHOT, irq_base, aod, &arizona->aod_irq_chip); if (ret != 0) { dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret); goto err_domain; } ret = regmap_add_irq_chip(arizona->regmap, arizona->virq[1], IRQF_ONESHOT, irq_base + ARIZONA_NUM_IRQ, irq, &arizona->irq_chip); if (ret != 0) { dev_err(arizona->dev, "Failed to add IRQs: %d\n", ret); goto err_aod; } /* Make sure the boot done IRQ is unmasked for resumes */ i = arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE); ret = request_threaded_irq(i, NULL, arizona_boot_done, IRQF_ONESHOT, "Boot done", arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to request boot done %d: %d\n", arizona->irq, ret); goto err_boot_done; } /* Handle control interface errors in the core */ if (ctrlif_error) { i = arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR); ret = request_threaded_irq(i, NULL, arizona_ctrlif_err, IRQF_ONESHOT, "Control interface error", arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to request CTRLIF_ERR %d: %d\n", arizona->irq, ret); goto err_ctrlif; } } ret = request_threaded_irq(arizona->irq, NULL, arizona_irq_thread, flags, "arizona", arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to request IRQ %d: %d\n", arizona->irq, ret); goto err_main_irq; } return 0; err_main_irq: free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona); err_ctrlif: free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona); err_boot_done: regmap_del_irq_chip(arizona->virq[1], arizona->irq_chip); err_aod: regmap_del_irq_chip(arizona->virq[0], arizona->aod_irq_chip); err_domain: err: return ret; }
static inline void tegra30_apbif_write(u32 reg, u32 val) { regmap_write(ahub->regmap_apbif, reg, val); }
static int arizona_apply_hardware_patch(struct arizona* arizona) { unsigned int fll, sysclk; int ret; /* Cache existing FLL and SYSCLK settings */ ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll); if (ret < 0) { dev_err(arizona->dev, "Failed to cache FLL settings: %d\n", ret); return ret; } ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk); if (ret < 0) { dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n", ret); return ret; } /* Start up SYSCLK using the FLL in free running mode */ ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN); if (ret < 0) { dev_err(arizona->dev, "Failed to start FLL in freerunning mode: %d\n", ret); return ret; } ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5, ARIZONA_FLL1_CLOCK_OK_STS, ARIZONA_FLL1_CLOCK_OK_STS); if (ret < 0) { ret = -ETIMEDOUT; goto err_fll; } ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144); if (ret < 0) { dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret); goto err_fll; } /* Start the write sequencer and wait for it to finish */ ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0, ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160); if (ret < 0) { dev_err(arizona->dev, "Failed to start write sequencer: %d\n", ret); goto err_sysclk; } ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1, ARIZONA_WSEQ_BUSY, 0); if (ret < 0) { regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0, ARIZONA_WSEQ_ABORT); ret = -ETIMEDOUT; } err_sysclk: ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk); if (ret < 0) dev_err(arizona->dev, "Failed to re-apply old SYSCLK settings: %d\n", ret); err_fll: ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll); if (ret < 0) dev_err(arizona->dev, "Failed to re-apply old FLL settings: %d\n", ret); return ret; }
static void hp_zcd_disable(struct snd_soc_component *cmpnt) { regmap_write(cmpnt->regmap, MT6351_ZCD_CON0, 0x0000); }
static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data) { struct snd_pcm_substream *substream = data; struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; struct lpass_data *drvdata = snd_soc_platform_get_drvdata(soc_runtime->platform); unsigned int interrupts; irqreturn_t ret = IRQ_NONE; int rv; rv = regmap_read(drvdata->lpaif_map, LPAIF_IRQSTAT_REG(LPAIF_IRQ_PORT_HOST), &interrupts); if (rv) { dev_err(soc_runtime->dev, "%s() error reading from irqstat reg: %d\n", __func__, rv); return IRQ_NONE; } interrupts &= LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S); if (interrupts & LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S)) { rv = regmap_write(drvdata->lpaif_map, LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S)); if (rv) { dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", __func__, rv); return IRQ_NONE; } snd_pcm_period_elapsed(substream); ret = IRQ_HANDLED; } if (interrupts & LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S)) { rv = regmap_write(drvdata->lpaif_map, LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S)); if (rv) { dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", __func__, rv); return IRQ_NONE; } dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__); snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); ret = IRQ_HANDLED; } if (interrupts & LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S)) { rv = regmap_write(drvdata->lpaif_map, LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S)); if (rv) { dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", __func__, rv); return IRQ_NONE; } dev_err(soc_runtime->dev, "%s() bus access error\n", __func__); snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); ret = IRQ_HANDLED; } return ret; }
/** * si476x_core_start() - early chip startup function * @core: Core device structure * @soft: When set, this flag forces "soft" startup, where "soft" * power down is the one done by sending appropriate command instead * of using reset pin of the tuner * * Perform required startup sequence to correctly power * up the chip and perform initial configuration. It does the * following sequence of actions: * 1. Claims and enables the power supplies VD and VIO1 required * for I2C interface of the chip operation. * 2. Waits for 100us, pulls the reset line up, enables irq, * waits for another 100us as it is specified by the * datasheet. * 3. Sends 'POWER_UP' command to the device with all provided * information about power-up parameters. * 4. Configures, pin multiplexor, disables digital audio and * configures interrupt sources. * * The function returns zero in case of succes or negative error code * otherwise. */ int si476x_core_start(struct si476x_core *core, bool soft) { struct i2c_client *client = core->client; int err; if (!soft) { if (gpio_is_valid(core->gpio_reset)) gpio_set_value_cansleep(core->gpio_reset, 1); if (client->irq) enable_irq(client->irq); udelay(100); if (!client->irq) { atomic_set(&core->is_alive, 1); si476x_core_schedule_polling_work(core); } } else { if (client->irq) enable_irq(client->irq); else { atomic_set(&core->is_alive, 1); si476x_core_schedule_polling_work(core); } } err = si476x_core_cmd_power_up(core, &core->power_up_parameters); if (err < 0) { dev_err(&core->client->dev, "Power up failure(err = %d)\n", err); goto disable_irq; } if (client->irq) atomic_set(&core->is_alive, 1); err = si476x_core_config_pinmux(core); if (err < 0) { dev_err(&core->client->dev, "Failed to configure pinmux(err = %d)\n", err); goto disable_irq; } if (client->irq) { err = regmap_write(core->regmap, SI476X_PROP_INT_CTL_ENABLE, SI476X_RDSIEN | SI476X_STCIEN | SI476X_CTSIEN); if (err < 0) { dev_err(&core->client->dev, "Failed to configure interrupt sources" "(err = %d)\n", err); goto disable_irq; } } return 0; disable_irq: if (err == -ENODEV) atomic_set(&core->is_alive, 0); if (client->irq) disable_irq(client->irq); else cancel_delayed_work_sync(&core->status_monitor); if (gpio_is_valid(core->gpio_reset)) gpio_set_value_cansleep(core->gpio_reset, 0); return err; }
/* * Note: CS53L30 counts the slot number per byte while ASoC counts the slot * number per slot_width. So there is a difference between the slots of ASoC * and the slots of CS53L30. */ static int cs53l30_set_dai_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) { struct cs53l30_private *priv = snd_soc_codec_get_drvdata(dai->codec); unsigned int loc[CS53L30_TDM_SLOT_MAX] = {48, 48, 48, 48}; unsigned int slot_next, slot_step; u64 tx_enable = 0; int i; if (!rx_mask) { dev_err(dai->dev, "rx masks must not be 0\n"); return -EINVAL; } /* Assuming slot_width is not supposed to be greater than 64 */ if (slots <= 0 || slot_width <= 0 || slot_width > 64) { dev_err(dai->dev, "invalid slot number or slot width\n"); return -EINVAL; } if (slot_width & 0x7) { dev_err(dai->dev, "slot width must count in byte\n"); return -EINVAL; } /* How many bytes in each ASoC slot */ slot_step = slot_width >> 3; for (i = 0; rx_mask && i < CS53L30_TDM_SLOT_MAX; i++) { /* Find the first slot from LSB */ slot_next = __ffs(rx_mask); /* Save the slot location by converting to CS53L30 slot */ loc[i] = slot_next * slot_step; /* Create the mask of CS53L30 slot */ tx_enable |= (u64)((u64)(1 << slot_step) - 1) << (u64)loc[i]; /* Clear this slot from rx_mask */ rx_mask &= ~(1 << slot_next); } /* Error out to avoid slot shift */ if (rx_mask && i == CS53L30_TDM_SLOT_MAX) { dev_err(dai->dev, "rx_mask exceeds max slot number: %d\n", CS53L30_TDM_SLOT_MAX); return -EINVAL; } /* Validate the last active CS53L30 slot */ slot_next = loc[i - 1] + slot_step - 1; if (slot_next > 47) { dev_err(dai->dev, "slot selection out of bounds: %u\n", slot_next); return -EINVAL; } for (i = 0; i < CS53L30_TDM_SLOT_MAX && loc[i] != 48; i++) { regmap_update_bits(priv->regmap, CS53L30_ASP_TDMTX_CTL(i), CS53L30_ASP_CHx_TX_LOC_MASK, loc[i]); dev_dbg(dai->dev, "loc[%d]=%x\n", i, loc[i]); } for (i = 0; i < CS53L30_ASP_TDMTX_ENx_MAX && tx_enable; i++) { regmap_write(priv->regmap, CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff); tx_enable >>= 8; dev_dbg(dai->dev, "en_reg=%x, tx_enable=%llx\n", CS53L30_ASP_TDMTX_ENx(i), tx_enable & 0xff); } return 0; }
static int tmp102_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct device *dev = &client->dev; struct device *hwmon_dev; struct tmp102 *tmp102; unsigned int regval; int err; if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA)) { dev_err(dev, "adapter doesn't support SMBus word transactions\n"); return -ENODEV; } tmp102 = devm_kzalloc(dev, sizeof(*tmp102), GFP_KERNEL); if (!tmp102) return -ENOMEM; i2c_set_clientdata(client, tmp102); tmp102->regmap = devm_regmap_init_i2c(client, &tmp102_regmap_config); if (IS_ERR(tmp102->regmap)) return PTR_ERR(tmp102->regmap); err = regmap_read(tmp102->regmap, TMP102_CONF_REG, ®val); if (err < 0) { dev_err(dev, "error reading config register\n"); return err; } if ((regval & ~TMP102_CONFREG_MASK) != (TMP102_CONF_R0 | TMP102_CONF_R1)) { dev_err(dev, "unexpected config register value\n"); return -ENODEV; } tmp102->config_orig = regval; err = devm_add_action_or_reset(dev, tmp102_restore_config, tmp102); if (err) return err; regval &= ~TMP102_CONFIG_CLEAR; regval |= TMP102_CONFIG_SET; err = regmap_write(tmp102->regmap, TMP102_CONF_REG, regval); if (err < 0) { dev_err(dev, "error writing config register\n"); return err; } /* * Mark that we are not ready with data until the first * conversion is complete */ tmp102->ready_time = jiffies + msecs_to_jiffies(CONVERSION_TIME_MS); hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, tmp102, &tmp102_chip_info, NULL); if (IS_ERR(hwmon_dev)) { dev_dbg(dev, "unable to register hwmon device\n"); return PTR_ERR(hwmon_dev); } dev_info(dev, "initialized\n"); return 0; }
static int wm8804_soft_reset(struct wm8804_priv *wm8804) { return regmap_write(wm8804->regmap, WM8804_RST_DEVID1, 0x0); }
static void tmp102_restore_config(void *data) { struct tmp102 *tmp102 = data; regmap_write(tmp102->regmap, TMP102_CONF_REG, tmp102->config_orig); }
static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct bcm2835_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); unsigned int sampling_rate = params_rate(params); unsigned int data_length, data_delay, bclk_ratio; unsigned int ch1pos, ch2pos, mode, format; uint32_t csreg; /* * If a stream is already enabled, * the registers are already set properly. */ regmap_read(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, &csreg); if (csreg & (BCM2835_I2S_TXON | BCM2835_I2S_RXON)) return 0; /* * Adjust the data length according to the format. * We prefill the half frame length with an integer * divider of 2400 as explained at the clock settings. * Maybe it is overwritten there, if the Integer mode * does not apply. */ switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: data_length = 16; break; case SNDRV_PCM_FORMAT_S32_LE: data_length = 32; break; default: return -EINVAL; } /* If bclk_ratio already set, use that one. */ if (dev->bclk_ratio) bclk_ratio = dev->bclk_ratio; else /* otherwise calculate a fitting block ratio */ bclk_ratio = 2 * data_length; /* set target clock rate*/ clk_set_rate(dev->clk, sampling_rate * bclk_ratio); /* Setup the frame format */ format = BCM2835_I2S_CHEN; if (data_length > 24) format |= BCM2835_I2S_CHWEX; format |= BCM2835_I2S_CHWID((data_length-8)&0xf); switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: data_delay = 1; break; default: /* * TODO * Others are possible but are not implemented at the moment. */ dev_err(dev->dev, "%s:bad format\n", __func__); return -EINVAL; } ch1pos = data_delay; ch2pos = bclk_ratio / 2 + data_delay; switch (params_channels(params)) { case 2: format = BCM2835_I2S_CH1(format) | BCM2835_I2S_CH2(format); format |= BCM2835_I2S_CH1(BCM2835_I2S_CHPOS(ch1pos)); format |= BCM2835_I2S_CH2(BCM2835_I2S_CHPOS(ch2pos)); break; default: return -EINVAL; } /* * Set format for both streams. * We cannot set another frame length * (and therefore word length) anyway, * so the format will be the same. */ regmap_write(dev->i2s_regmap, BCM2835_I2S_RXC_A_REG, format); regmap_write(dev->i2s_regmap, BCM2835_I2S_TXC_A_REG, format); /* Setup the I2S mode */ mode = 0; if (data_length <= 16) { /* * Use frame packed mode (2 channels per 32 bit word) * We cannot set another frame length in the second stream * (and therefore word length) anyway, * so the format will be the same. */ mode |= BCM2835_I2S_FTXP | BCM2835_I2S_FRXP; } mode |= BCM2835_I2S_FLEN(bclk_ratio - 1); mode |= BCM2835_I2S_FSLEN(bclk_ratio / 2); /* Master or slave? */ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: /* CPU is master */ break; case SND_SOC_DAIFMT_CBM_CFS: /* * CODEC is bit clock master * CPU is frame master */ mode |= BCM2835_I2S_CLKM; break; case SND_SOC_DAIFMT_CBS_CFM: /* * CODEC is frame master * CPU is bit clock master */ mode |= BCM2835_I2S_FSM; break; case SND_SOC_DAIFMT_CBM_CFM: /* CODEC is master */ mode |= BCM2835_I2S_CLKM; mode |= BCM2835_I2S_FSM; break; default: dev_err(dev->dev, "%s:bad master\n", __func__); return -EINVAL; } /* * Invert clocks? * * The BCM approach seems to be inverted to the classical I2S approach. */ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_NB_NF: /* None. Therefore, both for BCM */ mode |= BCM2835_I2S_CLKI; mode |= BCM2835_I2S_FSI; break; case SND_SOC_DAIFMT_IB_IF: /* Both. Therefore, none for BCM */ break; case SND_SOC_DAIFMT_NB_IF: /* * Invert only frame sync. Therefore, * invert only bit clock for BCM */ mode |= BCM2835_I2S_CLKI; break; case SND_SOC_DAIFMT_IB_NF: /* * Invert only bit clock. Therefore, * invert only frame sync for BCM */ mode |= BCM2835_I2S_FSI; break; default: return -EINVAL; } regmap_write(dev->i2s_regmap, BCM2835_I2S_MODE_A_REG, mode); /* Setup the DMA parameters */ regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_CS_A_REG, BCM2835_I2S_RXTHR(1) | BCM2835_I2S_TXTHR(1) | BCM2835_I2S_DMAEN, 0xffffffff); regmap_update_bits(dev->i2s_regmap, BCM2835_I2S_DREQ_A_REG, BCM2835_I2S_TX_PANIC(0x10) | BCM2835_I2S_RX_PANIC(0x30) | BCM2835_I2S_TX(0x30) | BCM2835_I2S_RX(0x20), 0xffffffff); /* Clear FIFOs */ bcm2835_i2s_clear_fifos(dev, true, true); return 0; }
static int max98505_set_clock(struct max98505_priv *max98505, unsigned int rate) { unsigned int clock; unsigned int mdll; unsigned int n; unsigned int m; u8 dai_sr = 0; switch (max98505->sysclk) { case 6000000: clock = 0; mdll = MAX98505_MDLL_MULT_MCLKx16; break; case 11289600: clock = 1; mdll = MAX98505_MDLL_MULT_MCLKx8; break; case 12000000: clock = 0; mdll = MAX98505_MDLL_MULT_MCLKx8; break; case 12288000: clock = 2; mdll = MAX98505_MDLL_MULT_MCLKx8; break; default: dev_info(max98505->codec->dev, "unsupported sysclk %d\n", max98505->sysclk); return -EINVAL; } if (max98505_rate_value(rate, clock, &dai_sr, &n, &m)) return -EINVAL; /* * 1. set DAI_SR to correct LRCLK frequency */ regmap_update_bits(max98505->regmap, MAX98505_R01B_DAI_CLK_MODE2, MAX98505_DAI_SR_MASK, dai_sr << MAX98505_DAI_SR_SHIFT); /* * 2. set DAI m divider */ regmap_write(max98505->regmap, MAX98505_R01C_DAI_CLK_DIV_M_MSBS, m >> 8); regmap_write(max98505->regmap, MAX98505_R01D_DAI_CLK_DIV_M_LSBS, m & 0xFF); /* * 3. set DAI n divider */ regmap_write(max98505->regmap, MAX98505_R01E_DAI_CLK_DIV_N_MSBS, n >> 8); regmap_write(max98505->regmap, MAX98505_R01F_DAI_CLK_DIV_N_LSBS, n & 0xFF); /* * 4. set MDLL */ regmap_update_bits(max98505->regmap, MAX98505_R01A_DAI_CLK_MODE1, MAX98505_MDLL_MULT_MASK, mdll << MAX98505_MDLL_MULT_SHIFT); return 0; }
static __always_inline int max8971_write(struct max8971_io *io, u8 addr, u8 val) { unsigned int buf = (unsigned int)val; return regmap_write(io->regmap, (unsigned int)addr, buf); }
static int cs53l30_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { const struct device_node *np = client->dev.of_node; struct device *dev = &client->dev; struct cs53l30_private *cs53l30; unsigned int devid = 0; unsigned int reg; int ret = 0, i; u8 val; cs53l30 = devm_kzalloc(dev, sizeof(*cs53l30), GFP_KERNEL); if (!cs53l30) return -ENOMEM; for (i = 0; i < ARRAY_SIZE(cs53l30->supplies); i++) cs53l30->supplies[i].supply = cs53l30_supply_names[i]; ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs53l30->supplies), cs53l30->supplies); if (ret) { dev_err(dev, "failed to get supplies: %d\n", ret); return ret; } ret = regulator_bulk_enable(ARRAY_SIZE(cs53l30->supplies), cs53l30->supplies); if (ret) { dev_err(dev, "failed to enable supplies: %d\n", ret); return ret; } /* Reset the Device */ cs53l30->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(cs53l30->reset_gpio)) { ret = PTR_ERR(cs53l30->reset_gpio); goto error; } gpiod_set_value_cansleep(cs53l30->reset_gpio, 1); i2c_set_clientdata(client, cs53l30); cs53l30->mclk_rate = 0; cs53l30->regmap = devm_regmap_init_i2c(client, &cs53l30_regmap); if (IS_ERR(cs53l30->regmap)) { ret = PTR_ERR(cs53l30->regmap); dev_err(dev, "regmap_init() failed: %d\n", ret); goto error; } /* Initialize codec */ ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_AB, ®); devid = reg << 12; ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_CD, ®); devid |= reg << 4; ret = regmap_read(cs53l30->regmap, CS53L30_DEVID_E, ®); devid |= (reg & 0xF0) >> 4; if (devid != CS53L30_DEVID) { ret = -ENODEV; dev_err(dev, "Device ID (%X). Expected %X\n", devid, CS53L30_DEVID); goto error; } ret = regmap_read(cs53l30->regmap, CS53L30_REVID, ®); if (ret < 0) { dev_err(dev, "failed to get Revision ID: %d\n", ret); goto error; } /* Check if MCLK provided */ cs53l30->mclk = devm_clk_get(dev, "mclk"); if (IS_ERR(cs53l30->mclk)) { if (PTR_ERR(cs53l30->mclk) != -ENOENT) { ret = PTR_ERR(cs53l30->mclk); goto error; } /* Otherwise mark the mclk pointer to NULL */ cs53l30->mclk = NULL; } /* Fetch the MUTE control */ cs53l30->mute_gpio = devm_gpiod_get_optional(dev, "mute", GPIOD_OUT_HIGH); if (IS_ERR(cs53l30->mute_gpio)) { ret = PTR_ERR(cs53l30->mute_gpio); goto error; } if (cs53l30->mute_gpio) { /* Enable MUTE controls via MUTE pin */ regmap_write(cs53l30->regmap, CS53L30_MUTEP_CTL1, CS53L30_MUTEP_CTL1_MUTEALL); /* Flip the polarity of MUTE pin */ if (gpiod_is_active_low(cs53l30->mute_gpio)) regmap_update_bits(cs53l30->regmap, CS53L30_MUTEP_CTL2, CS53L30_MUTE_PIN_POLARITY, 0); } if (!of_property_read_u8(np, "cirrus,micbias-lvl", &val)) regmap_update_bits(cs53l30->regmap, CS53L30_MICBIAS_CTL, CS53L30_MIC_BIAS_CTRL_MASK, val); if (of_property_read_bool(np, "cirrus,use-sdout2")) cs53l30->use_sdout2 = true; dev_info(dev, "Cirrus Logic CS53L30, Revision: %02X\n", reg & 0xFF); ret = snd_soc_register_codec(dev, &cs53l30_driver, &cs53l30_dai, 1); if (ret) { dev_err(dev, "failed to register codec: %d\n", ret); goto error; } return 0; error: regulator_bulk_disable(ARRAY_SIZE(cs53l30->supplies), cs53l30->supplies); return ret; }
static int isl29018_chip_init(struct isl29018_chip *chip) { int status; if (chip->type == isl29035) { status = isl29035_detect(chip); if (status < 0) return status; } /* Code added per Intersil Application Note 1534: * When VDD sinks to approximately 1.8V or below, some of * the part's registers may change their state. When VDD * recovers to 2.25V (or greater), the part may thus be in an * unknown mode of operation. The user can return the part to * a known mode of operation either by (a) setting VDD = 0V for * 1 second or more and then powering back up with a slew rate * of 0.5V/ms or greater, or (b) via I2C disable all ALS/PROX * conversions, clear the test registers, and then rewrite all * registers to the desired values. * ... * FOR ISL29011, ISL29018, ISL29021, ISL29023 * 1. Write 0x00 to register 0x08 (TEST) * 2. Write 0x00 to register 0x00 (CMD1) * 3. Rewrite all registers to the desired values * * ISL29018 Data Sheet (FN6619.1, Feb 11, 2010) essentially says * the same thing EXCEPT the data sheet asks for a 1ms delay after * writing the CMD1 register. */ status = regmap_write(chip->regmap, ISL29018_REG_TEST, 0x0); if (status < 0) { dev_err(chip->dev, "Failed to clear isl29018 TEST reg.(%d)\n", status); return status; } /* See Intersil AN1534 comments above. * "Operating Mode" (COMMAND1) register is reprogrammed when * data is read from the device. */ status = regmap_write(chip->regmap, ISL29018_REG_ADD_COMMAND1, 0); if (status < 0) { dev_err(chip->dev, "Failed to clear isl29018 CMD1 reg.(%d)\n", status); return status; } usleep_range(1000, 2000); /* per data sheet, page 10 */ /* set defaults */ status = isl29018_set_scale(chip, chip->scale.scale, chip->scale.uscale); if (status < 0) { dev_err(chip->dev, "Init of isl29018 fails\n"); return status; } status = isl29018_set_integration_time(chip, isl29018_int_utimes[chip->type][chip->int_time]); if (status < 0) { dev_err(chip->dev, "Init of isl29018 fails\n"); return status; } return 0; }
static int tps65910_rtc_probe(struct platform_device *pdev) { struct tps65910 *tps65910 = NULL; struct tps65910_rtc *tps_rtc = NULL; int ret; int irq; u32 rtc_reg; tps65910 = dev_get_drvdata(pdev->dev.parent); tps_rtc = devm_kzalloc(&pdev->dev, sizeof(struct tps65910_rtc), GFP_KERNEL); if (!tps_rtc) return -ENOMEM; /* Clear pending interrupts */ ret = regmap_read(tps65910->regmap, TPS65910_RTC_STATUS, &rtc_reg); if (ret < 0) return ret; ret = regmap_write(tps65910->regmap, TPS65910_RTC_STATUS, rtc_reg); if (ret < 0) return ret; dev_dbg(&pdev->dev, "Enabling rtc-tps65910.\n"); /* Enable RTC digital power domain */ ret = regmap_update_bits(tps65910->regmap, TPS65910_DEVCTRL, DEVCTRL_RTC_PWDN_MASK, 0 << DEVCTRL_RTC_PWDN_SHIFT); if (ret < 0) return ret; rtc_reg = TPS65910_RTC_CTRL_STOP_RTC; ret = regmap_write(tps65910->regmap, TPS65910_RTC_CTRL, rtc_reg); if (ret < 0) return ret; platform_set_drvdata(pdev, tps_rtc); irq = platform_get_irq(pdev, 0); if (irq <= 0) { dev_warn(&pdev->dev, "Wake up is not possible as irq = %d\n", irq); return -ENXIO; } ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, tps65910_rtc_interrupt, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), &pdev->dev); if (ret < 0) { dev_err(&pdev->dev, "IRQ is not free.\n"); return ret; } tps_rtc->irq = irq; device_set_wakeup_capable(&pdev->dev, 1); tps_rtc->rtc = devm_rtc_device_register(&pdev->dev, pdev->name, &tps65910_rtc_ops, THIS_MODULE); if (IS_ERR(tps_rtc->rtc)) { ret = PTR_ERR(tps_rtc->rtc); dev_err(&pdev->dev, "RTC device register: err %d\n", ret); return ret; } return 0; }
static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream, int cmd) { struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; struct lpass_data *drvdata = snd_soc_platform_get_drvdata(soc_runtime->platform); int ret; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* clear status before enabling interrupts */ ret = regmap_write(drvdata->lpaif_map, LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S)); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", __func__, ret); return ret; } ret = regmap_update_bits(drvdata->lpaif_map, LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S), LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S)); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n", __func__, ret); return ret; } ret = regmap_update_bits(drvdata->lpaif_map, LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", __func__, ret); return ret; } break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ret = regmap_update_bits(drvdata->lpaif_map, LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_OFF); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", __func__, ret); return ret; } ret = regmap_update_bits(drvdata->lpaif_map, LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST), LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S), 0); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n", __func__, ret); return ret; } break; } return 0; }
static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; struct drm_display_mode *mode = &crtc->state->mode; unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index; unsigned long dcuclk; int ret; index = drm_crtc_index(crtc); dcuclk = clk_get_rate(fsl_dev->clk); div = dcuclk / mode->clock / 1000; /* Configure timings: */ hbp = mode->htotal - mode->hsync_end; hfp = mode->hsync_start - mode->hdisplay; hsw = mode->hsync_end - mode->hsync_start; vbp = mode->vtotal - mode->vsync_end; vfp = mode->vsync_start - mode->vdisplay; vsw = mode->vsync_end - mode->vsync_start; ret = regmap_write(fsl_dev->regmap, DCU_HSYN_PARA, DCU_HSYN_PARA_BP(hbp) | DCU_HSYN_PARA_PW(hsw) | DCU_HSYN_PARA_FP(hfp)); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_VSYN_PARA, DCU_VSYN_PARA_BP(vbp) | DCU_VSYN_PARA_PW(vsw) | DCU_VSYN_PARA_FP(vfp)); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_DISP_SIZE, DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) | DCU_DISP_SIZE_DELTA_X(mode->hdisplay)); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_SYN_POL, DCU_SYN_POL_INV_VS_LOW | DCU_SYN_POL_INV_HS_LOW); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_DCU_MODE, DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_THRESHOLD, DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) | DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) | DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL)); if (ret) goto set_failed; ret = regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG); if (ret) goto set_failed; return; set_failed: dev_err(dev->dev, "set DCU register failed\n"); }
static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; struct lpass_data *drvdata = snd_soc_platform_get_drvdata(soc_runtime->platform); snd_pcm_format_t format = params_format(params); unsigned int channels = params_channels(params); unsigned int regval; int bitwidth; int ret; bitwidth = snd_pcm_format_width(format); if (bitwidth < 0) { dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n", __func__, bitwidth); return bitwidth; } regval = LPAIF_RDMACTL_BURSTEN_INCR4 | LPAIF_RDMACTL_AUDINTF_MI2S | LPAIF_RDMACTL_FIFOWM_8; switch (bitwidth) { case 16: switch (channels) { case 1: case 2: regval |= LPAIF_RDMACTL_WPSCNT_ONE; break; case 4: regval |= LPAIF_RDMACTL_WPSCNT_TWO; break; case 6: regval |= LPAIF_RDMACTL_WPSCNT_THREE; break; case 8: regval |= LPAIF_RDMACTL_WPSCNT_FOUR; break; default: dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", __func__, bitwidth, channels); return -EINVAL; } break; case 24: case 32: switch (channels) { case 1: regval |= LPAIF_RDMACTL_WPSCNT_ONE; break; case 2: regval |= LPAIF_RDMACTL_WPSCNT_TWO; break; case 4: regval |= LPAIF_RDMACTL_WPSCNT_FOUR; break; case 6: regval |= LPAIF_RDMACTL_WPSCNT_SIX; break; case 8: regval |= LPAIF_RDMACTL_WPSCNT_EIGHT; break; default: dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", __func__, bitwidth, channels); return -EINVAL; } break; default: dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", __func__, bitwidth, channels); return -EINVAL; } ret = regmap_write(drvdata->lpaif_map, LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), regval); if (ret) { dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", __func__, ret); return ret; } return 0; }
/** * wm8994_reg_write: Write a single WM8994 register. * * @wm8994: Device to write to. * @reg: Register to write to. * @val: Value to write. */ int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg, unsigned short val) { return regmap_write(wm8994->regmap, reg, val); }
static inline void tegra30_audio_write(u32 reg, u32 val) { regmap_write(ahub->regmap_ahub, reg, val); }
static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int num_configs) { int i, ret; u32 reg; u32 pullup = 0; u32 tristate = 0; struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); if (pin >= ZYNQ_NUM_MIOS) return -ENOTSUPP; ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®); if (ret) return -EIO; for (i = 0; i < num_configs; i++) { unsigned int param = pinconf_to_config_param(configs[i]); unsigned int arg = pinconf_to_config_argument(configs[i]); switch (param) { case PIN_CONFIG_BIAS_PULL_UP: pullup = ZYNQ_PINCONF_PULLUP; break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: tristate = ZYNQ_PINCONF_TRISTATE; break; case PIN_CONFIG_BIAS_DISABLE: reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); break; case PIN_CONFIG_SLEW_RATE: if (arg) reg |= ZYNQ_PINCONF_SPEED; else reg &= ~ZYNQ_PINCONF_SPEED; break; case PIN_CONFIG_IOSTANDARD: if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) { dev_warn(pctldev->dev, "unsupported IO standard '%u'\n", param); break; } reg &= ~ZYNQ_PINCONF_IOTYPE_MASK; reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT; break; case PIN_CONFIG_LOW_POWER_MODE: if (arg) reg |= ZYNQ_PINCONF_DISABLE_RECVR; else reg &= ~ZYNQ_PINCONF_DISABLE_RECVR; break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n", param); continue; } } if (tristate || pullup) { reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE); reg |= tristate | pullup; } ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg); if (ret) return -EIO; return 0; }
int __devinit arizona_dev_init(struct arizona *arizona) { struct device *dev = arizona->dev; const char *type_name; unsigned int reg, val; int (*apply_patch)(struct arizona *) = NULL; int ret, i; dev_set_drvdata(arizona->dev, arizona); mutex_init(&arizona->clk_lock); mutex_init(&arizona->reg_setting_lock); if (dev_get_platdata(arizona->dev)) memcpy(&arizona->pdata, dev_get_platdata(arizona->dev), sizeof(arizona->pdata)); regcache_cache_only(arizona->regmap, true); switch (arizona->type) { case WM5102: case WM5110: for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++) arizona->core_supplies[i].supply = wm5102_core_supplies[i]; arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies); break; default: dev_err(arizona->dev, "Unknown device type %d\n", arizona->type); return -EINVAL; } ret = mfd_add_devices(arizona->dev, -1, early_devs, ARRAY_SIZE(early_devs), NULL, 0); if (ret != 0) { dev_err(dev, "Failed to add early children: %d\n", ret); return ret; } ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies, arizona->core_supplies); if (ret != 0) { dev_err(dev, "Failed to request core supplies: %d\n", ret); goto err_early; } arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD"); if (IS_ERR(arizona->dcvdd)) { ret = PTR_ERR(arizona->dcvdd); dev_err(dev, "Failed to request DCVDD: %d\n", ret); goto err_early; } if (arizona->pdata.reset) { /* Start out with /RESET low to put the chip into reset */ ret = gpio_request_one(arizona->pdata.reset, GPIOF_DIR_OUT | GPIOF_INIT_LOW, "arizona /RESET"); if (ret != 0) { dev_err(dev, "Failed to request /RESET: %d\n", ret); goto err_early; } } ret = regulator_bulk_enable(arizona->num_core_supplies, arizona->core_supplies); if (ret != 0) { dev_err(dev, "Failed to enable core supplies: %d\n", ret); goto err_early; } ret = regulator_enable(arizona->dcvdd); if (ret != 0) { dev_err(dev, "Failed to enable DCVDD: %d\n", ret); goto err_enable; } if (arizona->pdata.control_init_time) msleep(arizona->pdata.control_init_time); if (arizona->pdata.reset) { gpio_set_value_cansleep(arizona->pdata.reset, 1); msleep(1); } regcache_cache_only(arizona->regmap, false); ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); if (ret != 0) { dev_err(dev, "Failed to read ID register: %d\n", ret); goto err_reset; } ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION, &arizona->rev); if (ret != 0) { dev_err(dev, "Failed to read revision register: %d\n", ret); goto err_reset; } arizona->rev &= ARIZONA_DEVICE_REVISION_MASK; switch (reg) { #ifdef CONFIG_MFD_WM5102 case 0x5102: type_name = "WM5102"; if (arizona->type != WM5102) { dev_err(arizona->dev, "WM5102 registered as %d\n", arizona->type); arizona->type = WM5102; } apply_patch = wm5102_patch; arizona->rev &= 0x7; break; #endif #ifdef CONFIG_MFD_WM5110 case 0x5110: type_name = "WM5110"; if (arizona->type != WM5110) { dev_err(arizona->dev, "WM5110 registered as %d\n", arizona->type); arizona->type = WM5110; } apply_patch = wm5110_patch; break; #endif default: dev_err(arizona->dev, "Unknown device ID %x\n", reg); goto err_reset; } dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A'); /* If we have a /RESET GPIO we'll already be reset */ if (!arizona->pdata.reset) { ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0); if (ret != 0) { dev_err(dev, "Failed to reset device: %d\n", ret); goto err_reset; } msleep(1); } switch (arizona->type) { case WM5102: ret = regmap_read(arizona->regmap, 0x19, &val); if (ret != 0) dev_err(dev, "Failed to check write sequencer state: %d\n", ret); else if (val & 0x01) break; /* Fall through */ default: ret = arizona_wait_for_boot(arizona); if (ret != 0) { dev_err(arizona->dev, "Device failed initial boot: %d\n", ret); goto err_reset; } break; } if (apply_patch) { ret = apply_patch(arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to apply patch: %d\n", ret); goto err_reset; } switch (arizona->type) { case WM5102: ret = arizona_apply_hardware_patch(arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to apply hardware patch: %d\n", ret); goto err_reset; } break; default: break; } } for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { if (!arizona->pdata.gpio_defaults[i]) continue; regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i, arizona->pdata.gpio_defaults[i]); } pm_runtime_enable(arizona->dev); /* Chip default */ if (!arizona->pdata.clk32k_src) arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2; switch (arizona->pdata.clk32k_src) { case ARIZONA_32KZ_MCLK1: case ARIZONA_32KZ_MCLK2: regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, arizona->pdata.clk32k_src - 1); arizona_clk32k_enable(arizona); break; case ARIZONA_32KZ_NONE: regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, 2); break; default: dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n", arizona->pdata.clk32k_src); ret = -EINVAL; goto err_reset; } for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) { if (!arizona->pdata.micbias[i].mV && !arizona->pdata.micbias[i].bypass) continue; /* Apply default for bypass mode */ if (!arizona->pdata.micbias[i].mV) arizona->pdata.micbias[i].mV = 2800; val = (arizona->pdata.micbias[i].mV - 1500) / 100; val <<= ARIZONA_MICB1_LVL_SHIFT; if (arizona->pdata.micbias[i].ext_cap) val |= ARIZONA_MICB1_EXT_CAP; if (arizona->pdata.micbias[i].discharge) val |= ARIZONA_MICB1_DISCH; if (arizona->pdata.micbias[i].fast_start) val |= ARIZONA_MICB1_RATE; if (arizona->pdata.micbias[i].bypass) val |= ARIZONA_MICB1_BYPASS; regmap_update_bits(arizona->regmap, ARIZONA_MIC_BIAS_CTRL_1 + i, ARIZONA_MICB1_LVL_MASK | ARIZONA_MICB1_DISCH | ARIZONA_MICB1_BYPASS | ARIZONA_MICB1_RATE, val); } for (i = 0; i < ARIZONA_MAX_INPUT; i++) { /* Default for both is 0 so noop with defaults */ val = arizona->pdata.dmic_ref[i] << ARIZONA_IN1_DMIC_SUP_SHIFT; val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT; regmap_update_bits(arizona->regmap, ARIZONA_IN1L_CONTROL + (i * 8), ARIZONA_IN1_DMIC_SUP_MASK | ARIZONA_IN1_MODE_MASK, val); } for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) { /* Default is 0 so noop with defaults */ if (arizona->pdata.out_mono[i]) val = ARIZONA_OUT1_MONO; else val = 0; regmap_update_bits(arizona->regmap, ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8), ARIZONA_OUT1_MONO, val); } for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) { if (arizona->pdata.spk_mute[i]) regmap_update_bits(arizona->regmap, ARIZONA_PDM_SPK1_CTRL_1 + (i * 2), ARIZONA_SPK1_MUTE_ENDIAN_MASK | ARIZONA_SPK1_MUTE_SEQ1_MASK, arizona->pdata.spk_mute[i]); if (arizona->pdata.spk_fmt[i]) regmap_update_bits(arizona->regmap, ARIZONA_PDM_SPK1_CTRL_2 + (i * 2), ARIZONA_SPK1_FMT_MASK, arizona->pdata.spk_fmt[i]); } /* set virtual IRQs */ arizona->virq[0] = arizona->pdata.irq_base; arizona->virq[1] = arizona->pdata.irq_base + ARIZONA_NUM_IRQ; switch (arizona->pdata.mic_spk_clamp) { case ARIZONA_MIC_CLAMP_SPKLN: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2, 0x3c, 0xc); break; case ARIZONA_MIC_CLAMP_SPKLP: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2, 0x3c, 0x1c); break; case ARIZONA_MIC_CLAMP_SPKRN: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3, 0x3c, 0xc); break; case ARIZONA_MIC_CLAMP_SPKRP: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3, 0x3c, 0x1c); break; default: break; } /* Set up for interrupts */ ret = arizona_irq_init(arizona); if (ret != 0) goto err_reset; arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error", arizona_clkgen_err, arizona); arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked", arizona_overclocked, arizona); arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked", arizona_underclocked, arizona); switch (arizona->type) { case WM5102: ret = mfd_add_devices(arizona->dev, -1, wm5102_devs, ARRAY_SIZE(wm5102_devs), NULL, 0); break; case WM5110: ret = mfd_add_devices(arizona->dev, -1, wm5110_devs, ARRAY_SIZE(wm5110_devs), NULL, 0); break; } if (ret != 0) { dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret); goto err_irq; } if (arizona->pdata.init_done) arizona->pdata.init_done(); #ifdef CONFIG_PM_RUNTIME regulator_disable(arizona->dcvdd); #endif return 0; err_irq: arizona_irq_exit(arizona); err_reset: if (arizona->pdata.reset) { gpio_set_value_cansleep(arizona->pdata.reset, 0); gpio_free(arizona->pdata.reset); } regulator_disable(arizona->dcvdd); err_enable: regulator_bulk_disable(arizona->num_core_supplies, arizona->core_supplies); err_early: mfd_remove_devices(dev); return ret; }
static int ds1343_probe(struct spi_device *spi) { struct ds1343_priv *priv; struct regmap_config config; unsigned int data; int res; memset(&config, 0, sizeof(config)); config.reg_bits = 8; config.val_bits = 8; config.write_flag_mask = 0x80; priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->spi = spi; mutex_init(&priv->mutex); /* RTC DS1347 works in spi mode 3 and * its chip select is active high */ spi->mode = SPI_MODE_3 | SPI_CS_HIGH; spi->bits_per_word = 8; res = spi_setup(spi); if (res) return res; spi_set_drvdata(spi, priv); priv->map = devm_regmap_init_spi(spi, &config); if (IS_ERR(priv->map)) { dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n"); return PTR_ERR(priv->map); } res = regmap_read(priv->map, DS1343_SECONDS_REG, &data); if (res) return res; regmap_read(priv->map, DS1343_CONTROL_REG, &data); data |= DS1343_INTCN; data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE); regmap_write(priv->map, DS1343_CONTROL_REG, data); regmap_read(priv->map, DS1343_STATUS_REG, &data); data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0); regmap_write(priv->map, DS1343_STATUS_REG, data); priv->rtc = devm_rtc_device_register(&spi->dev, "ds1343", &ds1343_rtc_ops, THIS_MODULE); if (IS_ERR(priv->rtc)) { dev_err(&spi->dev, "unable to register rtc ds1343\n"); return PTR_ERR(priv->rtc); } priv->irq = spi->irq; if (priv->irq >= 0) { res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, ds1343_thread, IRQF_NO_SUSPEND | IRQF_ONESHOT, "ds1343", priv); if (res) { priv->irq = -1; dev_err(&spi->dev, "unable to request irq for rtc ds1343\n"); } else { device_set_wakeup_capable(&spi->dev, 1); } } res = ds1343_sysfs_register(&spi->dev); if (res) dev_err(&spi->dev, "unable to create sysfs entries for rtc ds1343\n"); return 0; }
static int wm8523_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct wm8523_priv *wm8523; unsigned int val; int ret, i; wm8523 = devm_kzalloc(&i2c->dev, sizeof(struct wm8523_priv), GFP_KERNEL); if (wm8523 == NULL) return -ENOMEM; wm8523->regmap = devm_regmap_init_i2c(i2c, &wm8523_regmap); if (IS_ERR(wm8523->regmap)) { ret = PTR_ERR(wm8523->regmap); dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); return ret; } for (i = 0; i < ARRAY_SIZE(wm8523->supplies); i++) wm8523->supplies[i].supply = wm8523_supply_names[i]; ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8523->supplies), wm8523->supplies); if (ret != 0) { dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); return ret; } ret = regulator_bulk_enable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies); if (ret != 0) { dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); return ret; } ret = regmap_read(wm8523->regmap, WM8523_DEVICE_ID, &val); if (ret < 0) { dev_err(&i2c->dev, "Failed to read ID register\n"); goto err_enable; } if (val != 0x8523) { dev_err(&i2c->dev, "Device is not a WM8523, ID is %x\n", ret); ret = -EINVAL; goto err_enable; } ret = regmap_read(wm8523->regmap, WM8523_REVISION, &val); if (ret < 0) { dev_err(&i2c->dev, "Failed to read revision register\n"); goto err_enable; } dev_info(&i2c->dev, "revision %c\n", (val & WM8523_CHIP_REV_MASK) + 'A'); ret = regmap_write(wm8523->regmap, WM8523_DEVICE_ID, 0x8523); if (ret != 0) { dev_err(&i2c->dev, "Failed to reset device: %d\n", ret); goto err_enable; } regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies); i2c_set_clientdata(i2c, wm8523); ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_wm8523, &wm8523_dai, 1); return ret; err_enable: regulator_bulk_disable(ARRAY_SIZE(wm8523->supplies), wm8523->supplies); return ret; }
static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, unsigned int fmt, int fsl_dir) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); u32 val_cr2, val_cr4, reg_cr2, reg_cr4; if (fsl_dir == FSL_FMT_TRANSMITTER) { reg_cr2 = FSL_SAI_TCR2; reg_cr4 = FSL_SAI_TCR4; } else { reg_cr2 = FSL_SAI_RCR2; reg_cr4 = FSL_SAI_RCR4; } regmap_read(sai->regmap, reg_cr2, &val_cr2); regmap_read(sai->regmap, reg_cr4, &val_cr4); if (sai->big_endian_data) val_cr4 &= ~FSL_SAI_CR4_MF; else val_cr4 |= FSL_SAI_CR4_MF; /* DAI mode */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: /* * Frame low, 1clk before data, one word length for frame sync, * frame sync starts one serial clock cycle earlier, * that is, together with the last bit of the previous * data word. */ val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; break; case SND_SOC_DAIFMT_LEFT_J: /* * Frame high, one word length for frame sync, * frame sync asserts with the first bit of the frame. */ val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); break; case SND_SOC_DAIFMT_DSP_A: /* * Frame high, 1clk before data, one bit for frame sync, * frame sync starts one serial clock cycle earlier, * that is, together with the last bit of the previous * data word. */ val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr4 &= ~FSL_SAI_CR4_FSP; val_cr4 |= FSL_SAI_CR4_FSE; sai->is_dsp_mode = true; break; case SND_SOC_DAIFMT_DSP_B: /* * Frame high, one bit for frame sync, * frame sync asserts with the first bit of the frame. */ val_cr2 &= ~FSL_SAI_CR2_BCP; val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP); sai->is_dsp_mode = true; break; case SND_SOC_DAIFMT_RIGHT_J: /* To be done */ default: return -EINVAL; } /* DAI clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_IF: /* Invert both clocks */ val_cr2 ^= FSL_SAI_CR2_BCP; val_cr4 ^= FSL_SAI_CR4_FSP; break; case SND_SOC_DAIFMT_IB_NF: /* Invert bit clock */ val_cr2 ^= FSL_SAI_CR2_BCP; break; case SND_SOC_DAIFMT_NB_IF: /* Invert frame clock */ val_cr4 ^= FSL_SAI_CR4_FSP; break; case SND_SOC_DAIFMT_NB_NF: /* Nothing to do for both normal cases */ break; default: return -EINVAL; } /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: val_cr2 |= FSL_SAI_CR2_BCD_MSTR; val_cr4 |= FSL_SAI_CR4_FSD_MSTR; break; case SND_SOC_DAIFMT_CBM_CFM: val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR; val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR; break; case SND_SOC_DAIFMT_CBS_CFM: val_cr2 |= FSL_SAI_CR2_BCD_MSTR; val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR; break; case SND_SOC_DAIFMT_CBM_CFS: val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR; val_cr4 |= FSL_SAI_CR4_FSD_MSTR; break; default: return -EINVAL; } regmap_write(sai->regmap, reg_cr2, val_cr2); regmap_write(sai->regmap, reg_cr4, val_cr4); return 0; }
static int pmic8xxx_kpd_init(struct pmic8xxx_kp *kp, struct platform_device *pdev) { const struct device_node *of_node = pdev->dev.of_node; unsigned int scan_delay_ms; unsigned int row_hold_ns; unsigned int debounce_ms; int bits, rc, cycles; u8 scan_val = 0, ctrl_val = 0; static const u8 row_bits[] = { 0, 1, 2, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, }; /* Find column bits */ if (kp->num_cols < KEYP_CTRL_SCAN_COLS_MIN) bits = 0; else bits = kp->num_cols - KEYP_CTRL_SCAN_COLS_MIN; ctrl_val = (bits & KEYP_CTRL_SCAN_COLS_BITS) << KEYP_CTRL_SCAN_COLS_SHIFT; /* Find row bits */ if (kp->num_rows < KEYP_CTRL_SCAN_ROWS_MIN) bits = 0; else bits = row_bits[kp->num_rows - KEYP_CTRL_SCAN_ROWS_MIN]; ctrl_val |= (bits << KEYP_CTRL_SCAN_ROWS_SHIFT); rc = regmap_write(kp->regmap, KEYP_CTRL, ctrl_val); if (rc < 0) { dev_err(kp->dev, "Error writing KEYP_CTRL reg, rc=%d\n", rc); return rc; } if (of_property_read_u32(of_node, "scan-delay", &scan_delay_ms)) scan_delay_ms = MIN_SCAN_DELAY; if (scan_delay_ms > MAX_SCAN_DELAY || scan_delay_ms < MIN_SCAN_DELAY || !is_power_of_2(scan_delay_ms)) { dev_err(&pdev->dev, "invalid keypad scan time supplied\n"); return -EINVAL; } if (of_property_read_u32(of_node, "row-hold", &row_hold_ns)) row_hold_ns = MIN_ROW_HOLD_DELAY; if (row_hold_ns > MAX_ROW_HOLD_DELAY || row_hold_ns < MIN_ROW_HOLD_DELAY || ((row_hold_ns % MIN_ROW_HOLD_DELAY) != 0)) { dev_err(&pdev->dev, "invalid keypad row hold time supplied\n"); return -EINVAL; } if (of_property_read_u32(of_node, "debounce", &debounce_ms)) debounce_ms = MIN_DEBOUNCE_TIME; if (((debounce_ms % 5) != 0) || debounce_ms > MAX_DEBOUNCE_TIME || debounce_ms < MIN_DEBOUNCE_TIME) { dev_err(&pdev->dev, "invalid debounce time supplied\n"); return -EINVAL; } bits = (debounce_ms / 5) - 1; scan_val |= (bits << KEYP_SCAN_DBOUNCE_SHIFT); bits = fls(scan_delay_ms) - 1; scan_val |= (bits << KEYP_SCAN_PAUSE_SHIFT); /* Row hold time is a multiple of 32KHz cycles. */ cycles = (row_hold_ns * KEYP_CLOCK_FREQ) / NSEC_PER_SEC; scan_val |= (cycles << KEYP_SCAN_ROW_HOLD_SHIFT); rc = regmap_write(kp->regmap, KEYP_SCAN, scan_val); if (rc) dev_err(kp->dev, "Error writing KEYP_SCAN reg, rc=%d\n", rc); return rc; }
static irqreturn_t max98505_interrupt(int irq, void *data) { struct max98505_priv *max98505 = (struct max98505_priv *) data; unsigned int mask0; unsigned int mask1; unsigned int mask2; unsigned int flag0; unsigned int flag1; unsigned int flag2; regmap_read(max98505->regmap, MAX98505_R00B_IRQ_ENABLE0, &mask0); regmap_read(max98505->regmap, MAX98505_R008_FLAG0, &flag0); regmap_read(max98505->regmap, MAX98505_R00C_IRQ_ENABLE1, &mask1); regmap_read(max98505->regmap, MAX98505_R009_FLAG1, &flag1); regmap_read(max98505->regmap, MAX98505_R00D_IRQ_ENABLE2, &mask2); regmap_read(max98505->regmap, MAX98505_R00A_FLAG2, &flag2); flag0 &= mask0; flag1 &= mask1; flag2 &= mask2; if (!flag0 && !flag1 && !flag2) return IRQ_NONE; /* Send work to be scheduled */ if (flag0 & MAX98505_THERMWARN_END_STATE_MASK) msg_maxim("MAX98505_THERMWARN_STATE_MASK active!"); if (flag0 & MAX98505_THERMWARN_BGN_STATE_MASK) msg_maxim("MAX98505_THERMWARN_BGN_STATE_MASK active!"); if (flag0 & MAX98505_THERMSHDN_END_STATE_MASK) msg_maxim("MAX98505_THERMSHDN_END_STATE_MASK active!"); if (flag0 & MAX98505_THERMSHDN_BGN_STATE_MASK) msg_maxim("MAX98505_THERMSHDN_BGN_STATE_MASK active!"); if (flag1 & MAX98505_SPRCURNT_STATE_MASK) msg_maxim("MAX98505_SPRCURNT_STATE_MASK active!"); if (flag1 & MAX98505_WATCHFAIL_STATE_MASK) msg_maxim("MAX98505_WATCHFAIL_STATE_MASK active!"); if (flag1 & MAX98505_ALCINFH_STATE_MASK) msg_maxim("MAX98505_ALCINFH_STATE_MASK active!"); if (flag1 & MAX98505_ALCACT_STATE_MASK) msg_maxim("MAX98505_ALCACT_STATE_MASK active!"); if (flag1 & MAX98505_ALCMUT_STATE_MASK) msg_maxim("MAX98505_ALCMUT_STATE_MASK active!"); if (flag1 & MAX98505_ALCP_STATE_MASK) msg_maxim("MAX98505_ALCP_STATE_MASK active!"); if (flag2 & MAX98505_SLOTOVRN_STATE_MASK) msg_maxim("MAX98505_SLOTOVRN_STATE_MASK active!"); if (flag2 & MAX98505_INVALSLOT_STATE_MASK) msg_maxim("MAX98505_INVALSLOT_STATE_MASK active!"); if (flag2 & MAX98505_SLOTCNFLT_STATE_MASK) msg_maxim("MAX98505_SLOTCNFLT_STATE_MASK active!"); if (flag2 & MAX98505_VBSTOVFL_STATE_MASK) msg_maxim("MAX98505_VBSTOVFL_STATE_MASK active!"); if (flag2 & MAX98505_VBATOVFL_STATE_MASK) msg_maxim("MAX98505_VBATOVFL_STATE_MASK active!"); if (flag2 & MAX98505_IMONOVFL_STATE_MASK) msg_maxim("MAX98505_IMONOVFL_STATE_MASK active!"); if (flag2 & MAX98505_VMONOVFL_STATE_MASK) msg_maxim("MAX98505_VMONOVFL_STATE_MASK active!"); regmap_write(max98505->regmap, MAX98505_R00E_IRQ_CLEAR0, flag0&0xff); regmap_write(max98505->regmap, MAX98505_R00F_IRQ_CLEAR1, flag1&0xff); regmap_write(max98505->regmap, MAX98505_R010_IRQ_CLEAR2, flag2&0xff); return IRQ_HANDLED; }