void main(void) { timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); timestamp_add_now(TS_END_ROMSTAGE); run_ramstage(); }
void main(void) { #if CONFIG_COLLECT_TIMESTAMPS uint64_t start_romstage_time; uint64_t before_dram_time; uint64_t after_dram_time; uint64_t base_time = timestamp_get(); start_romstage_time = timestamp_get(); #endif console_init(); configure_l2ctlr(); tsadc_init(); /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS before_dram_time = timestamp_get(); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS after_dram_time = timestamp_get(); #endif /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); mmu_config_range((uintptr_t)_dma_coherent/MiB, _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); #if CONFIG_COLLECT_TIMESTAMPS timestamp_init(base_time); timestamp_add(TS_START_ROMSTAGE, start_romstage_time); timestamp_add(TS_BEFORE_INITRAM, before_dram_time); timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) void *entry = vboot2_load_ramstage(); if (entry != NULL) stage_exit(entry); #endif run_ramstage(); }