/* This function will configure the window size to be capture in CCDC reg */
static void ccdc_setwin(struct v4l2_rect *image_win,
enum ccdc_frmfmt frm_fmt, int ppc, int mode)
{
int horz_start, horz_nr_pixels;
int vert_start, vert_nr_lines;
int mid_img = 0;
dev_dbg(dev, "\nStarting ccdc_setwin...");
/**
* ppc - per pixel count. indicates how many pixels per cell
* output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
* raw capture this is 1
*/
horz_start = image_win->left << (ppc - 1);
horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
/* Writing the horizontal info into the registers */
regw(horz_start & START_PX_HOR_MASK, SPH);
regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH);
vert_start = image_win->top;
if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
vert_nr_lines = (image_win->height >> 1) - 1;
vert_start >>= 1;
/* To account for VD since line 0 doesn't have any data */
vert_start += 1;
} else {
/* vpif_set_mode_info:
* This function is used to set horizontal and vertical config parameters
* As per the standard in the channel, configure the values of L1, L3,
* L5, L7 L9, L11 in VPIF Register , also write width and height
*/
static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
u8 channel_id, u8 config_channel_id)
{
u32 value;
value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
regw(value, vpifregs[channel_id].h_cfg);
value = (config->l1 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l3 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_00);
value = (config->l5 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l7 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_01);
value = (config->l9 & vpifregs[config_channel_id].len_mask);
value <<= VPIF_CH_LEN_SHIFT;
value |= (config->l11 & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg_02);
value = (config->vsize & vpifregs[config_channel_id].len_mask);
regw(value, vpifregs[channel_id].v_cfg);
}
static void ccdc_reset(void)
{
int i, clkctrl;
/* disable CCDC */
printk(KERN_DEBUG "\nstarting ccdc_reset...");
ccdc_enable(0);
/* set all registers to default value */
for (i = 0; i <= 0x15c; i += 4)
regw(0, i);
/* no culling support */
regw(0xffff, CULH);
regw(0xff, CULV);
/* Set default Gain and Offset */
ccdc_hw_params_raw.gain.r_ye = 256;
ccdc_hw_params_raw.gain.gb_g = 256;
ccdc_hw_params_raw.gain.gr_cy = 256;
ccdc_hw_params_raw.gain.b_mg = 256;
ccdc_hw_params_raw.ccdc_offset = 0;
ccdc_config_gain_offset();
/* up to 12 bit sensor */
regw(0x0FFF, OUTCLIP);
vpss_dfc_memory_sel(VPSS_DFC_SEL_IPIPE);
regw_bl(0x00, CCDCMUX); /*CCDC input Mux select directly from sensor */
clkctrl = regr_bl(CLKCTRL);
clkctrl &= 0x3f;
clkctrl |= 0x40;
regw_bl(clkctrl, CLKCTRL);
printk(KERN_DEBUG "\nEnd of ccdc_reset...");
}
static void ccdc_restore_defaults(void)
{
enum vpss_ccdc_source_sel source = VPSS_CCDCIN;
int i;
memcpy(&ccdc_cfg.bayer.config_params, &ccdc_config_defaults,
sizeof(struct ccdc_config_params_raw));
dev_dbg(dev, "\nstarting ccdc_restore_defaults...");
/* Enable clock to ISIF, IPIPEIF and BL */
vpss_enable_clock(VPSS_CCDC_CLOCK, 1);
vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1);
vpss_enable_clock(VPSS_BL_CLOCK, 1);
/* set all registers to default value */
for (i = 0; i <= 0x1f8; i += 4)
regw(0, i);
/* no culling support */
regw(0xffff, CULH);
regw(0xff, CULV);
/* Set default offset and gain */
ccdc_config_gain_offset();
vpss_select_ccdc_source(source);
dev_dbg(dev, "\nEnd of ccdc_restore_defaults...");
}
/*
* vdce_interrupt set : Function to set interrupt
*/
inline int vdce_enable_int(void)
{
regw(1, VDCE_INTEN);
regw(1, VDCE_INTEN_SET);
/* Disable emulation control signal */
regw(1, VDCE_EMULATION_CTRL);
return 0;
}
static void ccdc_config_gain_offset(void)
{
/* configure gain */
regw(ccdc_hw_params_raw.gain.r_ye, RYEGAIN);
regw(ccdc_hw_params_raw.gain.gr_cy, GRCYGAIN);
regw(ccdc_hw_params_raw.gain.gb_g, GBGGAIN);
regw(ccdc_hw_params_raw.gain.b_mg, BMGGAIN);
/* configure offset */
regw(ccdc_hw_params_raw.ccdc_offset, OFFSET);
}
static void ccdc_disable_all_modules(void)
{
/* disable BC */
regw(0, CLAMPCFG);
/* disable vdfc */
regw(0, DFCCTL);
/* disable CSC */
regw(0, CSCCTL);
/* disable linearization */
regw(0, LINCFG0);
/* disable other modules here as they are supported */
}
/* config_vpif_params
* Function to set the parameters of a channel
* Mainly modifies the channel ciontrol register
* It sets frame format, yc mux mode
*/
static void config_vpif_params(struct vpif_params *vpifparams,
u8 channel_id, u8 found)
{
const struct vpif_channel_config_params *config = &vpifparams->std_info;
u32 value, ch_nip, reg;
u8 start, end;
int i;
start = channel_id;
end = channel_id + found;
for (i = start; i < end; i++) {
reg = vpifregs[i].ch_ctrl;
if (channel_id < 2)
ch_nip = VPIF_CAPTURE_CH_NIP;
else
ch_nip = VPIF_DISPLAY_CH_NIP;
vpif_wr_bit(reg, ch_nip, config->frm_fmt);
vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
vpifparams->video_params.storage_mode);
/* Set raster scanning SDR Format */
vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
if (channel_id > 1) /* Set the Pixel enable bit */
vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
else if (config->capture_format) {
/* Set the polarity of various pins */
vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
vpifparams->iface.fid_pol);
vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
vpifparams->iface.vd_pol);
vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
vpifparams->iface.hd_pol);
value = regr(reg);
/* Set data width */
value &= ((~(unsigned int)(0x3)) <<
VPIF_CH_DATA_WIDTH_BIT);
value |= ((vpifparams->params.data_sz) <<
VPIF_CH_DATA_WIDTH_BIT);
regw(value, reg);
}
/* Write the pitch in the driver */
regw((vpifparams->video_params.hpitch),
vpifregs[i].line_offset);
}
}
static inline u32 ccdc_merge(u32 mask, u32 val, u32 offset)
{
u32 new_val = (regr(offset) & ~mask) | (val & mask);
regw(new_val, offset);
return new_val;
}
static void ccdc_config_culling(struct ccdc_cul *cul)
{
u32 val;
/* Horizontal pattern */
val = (cul->hcpat_even) << CULL_PAT_EVEN_LINE_SHIFT;
val |= cul->hcpat_odd;
regw(val, CULH);
/* vertical pattern */
regw(cul->vcpat, CULV);
/* LPF */
ccdc_merge((CCDC_LPF_MASK << CCDC_LPF_SHIFT),
(cul->en_lpf << CCDC_LPF_SHIFT), MODESET);
}
static void ccdc_enable(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~0x1);
temp |= (en & 0x01);
regw(temp, SYNCEN);
}
static void ccdc_enable_output_to_sdram(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~(0x1 << 1));
temp |= (en & 0x01) << 1;
regw(temp, SYNCEN);
}
static void ccdc_enable(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
regw(temp, SYNCEN);
}
static void ccdc_enable_output_to_sdram(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~(CCDC_SYNCEN_WEN_MASK));
temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
regw(temp, SYNCEN);
}
/* vpif_set_video_params
* This function is used to set video parameters in VPIF register
*/
int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
{
const struct vpif_channel_config_params *config = &vpifparams->std_info;
int found = 1;
vpif_set_mode_info(config, channel_id, channel_id);
if (!config->ycmux_mode) {
/* YC are on separate channels (HDTV formats) */
vpif_set_mode_info(config, channel_id + 1, channel_id);
found = 2;
}
config_vpif_params(vpifparams, channel_id, found);
regw(0x80, VPIF_REQ_SIZE);
regw(0x01, VPIF_EMULATION_CTRL);
return found;
}
static void ccdc_config_gain_offset(void)
{
struct ccdc_gain_offsets_adj *gain_off_ptr =
&ccdc_cfg.bayer.config_params.gain_offset;
u32 val;
val = ((gain_off_ptr->gain_sdram_en & 1) << GAIN_SDRAM_EN_SHIFT) |
((gain_off_ptr->gain_ipipe_en & 1) << GAIN_IPIPE_EN_SHIFT) |
((gain_off_ptr->gain_h3a_en & 1) << GAIN_H3A_EN_SHIFT) |
((gain_off_ptr->offset_sdram_en & 1) << OFST_SDRAM_EN_SHIFT) |
((gain_off_ptr->offset_ipipe_en & 1) << OFST_IPIPE_EN_SHIFT) |
((gain_off_ptr->offset_h3a_en & 1) << OFST_H3A_EN_SHIFT);
ccdc_merge(GAIN_OFFSET_EN_MASK, val, CGAMMAWD);
val = ((gain_off_ptr->gain.r_ye.integer & GAIN_INTEGER_MASK)
<< GAIN_INTEGER_SHIFT);
val |= (ccdc_cfg.bayer.
config_params.gain_offset.gain.r_ye.decimal &
GAIN_DECIMAL_MASK);
regw(val, CRGAIN);
val = ((gain_off_ptr->gain.gr_cy
.integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
val |= (gain_off_ptr->gain.gr_cy
.decimal & GAIN_DECIMAL_MASK);
regw(val, CGRGAIN);
val = ((gain_off_ptr->gain.gb_g
.integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
val |= (gain_off_ptr->gain.gb_g
.decimal & GAIN_DECIMAL_MASK);
regw(val, CGBGAIN);
val = ((gain_off_ptr->gain.b_mg
.integer & GAIN_INTEGER_MASK) << GAIN_INTEGER_SHIFT);
val |= (gain_off_ptr->gain.b_mg
.decimal & GAIN_DECIMAL_MASK);
regw(val, CBGAIN);
regw((gain_off_ptr->offset &
OFFSET_MASK), COFSTA);
}
/*
* ccdc_restore_defaults()
* This function restore power on defaults in the ccdc registers
*/
static int ccdc_restore_defaults(void)
{
int i;
dev_dbg(dev, "\nstarting ccdc_restore_defaults...");
/* set all registers to zero */
for (i = 0; i <= CCDC_REG_LAST; i += 4)
regw(0, i);
/* now override the values with power on defaults in registers */
regw(MODESET_DEFAULT, MODESET);
/* no culling support */
regw(CULH_DEFAULT, CULH);
regw(CULV_DEFAULT, CULV);
/* Set default Gain and Offset */
ccdc_hw_params_raw.gain.r_ye = GAIN_DEFAULT;
ccdc_hw_params_raw.gain.gb_g = GAIN_DEFAULT;
ccdc_hw_params_raw.gain.gr_cy = GAIN_DEFAULT;
ccdc_hw_params_raw.gain.b_mg = GAIN_DEFAULT;
ccdc_config_gain_offset();
regw(OUTCLIP_DEFAULT, OUTCLIP);
regw(LSCCFG2_DEFAULT, LSCCFG2);
/* select ccdc input */
if (vpss_select_ccdc_source(VPSS_CCDCIN)) {
dev_dbg(dev, "\ncouldn't select ccdc input source");
return -EFAULT;
}
/* select ccdc clock */
if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) {
dev_dbg(dev, "\ncouldn't enable ccdc clock");
return -EFAULT;
}
dev_dbg(dev, "\nEnd of ccdc_restore_defaults...");
return 0;
}
/*This function will configure the window size to be capture in CCDC reg */
void ccdc_setwin(ccdc_imgwin * image_win, ccdc_frmfmt frm_fmt, int ppc)
{
int horz_start, horz_nr_pixels;
int vert_start, vert_nr_lines;
int val = 0, mid_img = 0;
dev_dbg(vpfe_dev, "\nStarting ccdc_setwin...");
/* configure horizonal and vertical starts and sizes */
horz_start = image_win->left << (ppc - 1);
horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
HORZ_INFO);
vert_start = image_win->top;
if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
vert_nr_lines = (image_win->height >> 1) - 1;
vert_start >>= 1;
/* configure VDINT0 and VDINT1 */
val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
regw(val, VDINT);
} else {
void
dp8390getea(Ether* ether, uchar* ea)
{
Dp8390 *ctlr;
uchar cr;
int i;
ctlr = ether->ctlr;
/*
* Get the ethernet address from the chip.
* Take care to restore the command register
* afterwards.
*/
ilock(ctlr);
cr = regr(ctlr, Cr) & ~Txp;
regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
for(i = 0; i < Eaddrlen; i++)
ea[i] = regr(ctlr, Par0+i);
regw(ctlr, Cr, cr);
iunlock(ctlr);
}
void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
u8 channel_id)
{
u32 value;
value = 0x3F8 & (vbiparams->hstart0);
value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
regw(value, vpifregs[channel_id].vanc0_strt);
value = 0x3F8 & (vbiparams->hstart1);
value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
regw(value, vpifregs[channel_id].vanc1_strt);
value = 0x3F8 & (vbiparams->hsize0);
value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
regw(value, vpifregs[channel_id].vanc0_size);
value = 0x3F8 & (vbiparams->hsize1);
value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
regw(value, vpifregs[channel_id].vanc1_size);
}
/*
* ======== ccdc_setwin ========
*
* This function will configure the window size to
* be capture in CCDC reg
*/
static void ccdc_setwin(struct ccdc_imgwin *image_win,
enum ccdc_frmfmt frm_fmt, int ppc, int mode)
{
int horz_start, horz_nr_pixels;
int vert_start, vert_nr_lines;
int mid_img = 0;
printk(KERN_DEBUG "\nStarting ccdc_setwin...");
/* configure horizonal and vertical starts and sizes */
horz_start = image_win->left << (ppc - 1);
horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
/*Writing the horizontal info into the registers */
regw(horz_start & START_PX_HOR_MASK, SPH);
regw(horz_nr_pixels & NUM_PX_HOR_MASK, NPH);
vert_start = image_win->top;
if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
vert_nr_lines = (image_win->height >> 1) - 1;
vert_start >>= 1;
/* Since first line doesn't have any data */
vert_start += 1;
} else {
void
dp8390setea(Ether* ether)
{
int i;
uchar cr;
Dp8390 *ctlr;
ctlr = ether->ctlr;
/*
* Set the ethernet address into the chip.
* Take care to restore the command register
* afterwards. Don't care about multicast
* addresses as multicast is never enabled
* (currently).
*/
ilock(ctlr);
cr = regr(ctlr, Cr) & ~Txp;
regw(ctlr, Cr, Page1|(~(Ps1|Ps0) & cr));
for(i = 0; i < Eaddrlen; i++)
regw(ctlr, Par0+i, ether->ea[i]);
regw(ctlr, Cr, cr);
iunlock(ctlr);
}
/*
* vdce_enable : Function to enable the ge module
*/
int vdce_enable(vdce_hw_config_t * register_config)
{
dev_dbg(vdce_device, " vdce_enable E\n");
/* enabling the resizer the setting enable bit */
register_config->vdce_ctrl =
BITSET(register_config->vdce_ctrl, VDCE_ENABLE);
regw(register_config->vdce_ctrl, VDCE_CTRL);
register_config->vdce_ctrl =
BITRESET(register_config->vdce_ctrl, VDCE_ENABLE);
dev_dbg(vdce_device, "vdce enable L\n");
return 0;
}
static void*
_dp8390read(Dp8390* ctlr, void* to, ulong from, ulong len)
{
uchar cr;
int timo;
/*
* Read some data at offset 'from' in the card's memory
* using the DP8390 remote DMA facility, and place it at
* 'to' in main memory, via the I/O data port.
*/
cr = regr(ctlr, Cr) & ~Txp;
regw(ctlr, Cr, Page0|RdABORT|Sta);
regw(ctlr, Isr, Rdc);
/*
* Set up the remote DMA address and count.
*/
len = ROUNDUP(len, ctlr->width);
regw(ctlr, Rbcr0, len & 0xFF);
regw(ctlr, Rbcr1, (len>>8) & 0xFF);
regw(ctlr, Rsar0, from & 0xFF);
regw(ctlr, Rsar1, (from>>8) & 0xFF);
/*
* Start the remote DMA read and suck the data
* out of the I/O port.
*/
regw(ctlr, Cr, Page0|RdREAD|Sta);
rdread(ctlr, to, len);
/*
* Wait for the remote DMA to complete. The timeout
* is necessary because this routine may be called on
* a non-existent chip during initialisation and, due
* to the miracles of the bus, it's possible to get this
* far and still be talking to a slot full of nothing.
*/
for(timo = 10000; (regr(ctlr, Isr) & Rdc) == 0 && timo; timo--)
;
regw(ctlr, Isr, Rdc);
regw(ctlr, Cr, cr);
return to;
}
/* Function to enable/ disable AEW Engine */
inline void aew_engine_setup(int value)
{
unsigned int pcr;
dev_dbg(aewdev, __FUNCTION__ "E\n");
dev_dbg(aewdev, "\nAEW_REG(PCR) Before Setting %x", regr(AEWPCR));
/* Read Pcr Register */
pcr = regr(AEWPCR);
pcr &= ~AEW_EN;
pcr |= (value << AEW_EN_SHIFT);
/*Set AF_EN bit in PCR Register */
regw(pcr, AEWPCR);
dev_dbg(aewdev, "\nAfter Setting %d : PCR VALUE %x", value,
regr(AEWPCR));
dev_dbg(aewdev, __FUNCTION__ "L\n");
}
void ccdc_reset()
{
int i;
/* disable CCDC */
ccdc_enable(0);
/* set all registers to default value */
for (i = 0; i <= 0x94; i += 4) {
regw(0, i);
}
regw(0, PCR);
regw(0, SYN_MODE);
regw(0, HD_VD_WID);
regw(0, PIX_LINES);
regw(0, HORZ_INFO);
regw(0, VERT_START);
regw(0, VERT_LINES);
regw(0xffff00ff, CULLING);
regw(0, HSIZE_OFF);
regw(0, SDOFST);
regw(0, SDR_ADDR);
regw(0, VDINT);
regw(0, REC656IF);
regw(0, CCDCFG);
regw(0, FMTCFG);
regw(0, VP_OUT);
}
/*
* vdce_hardware_setup :Function to set GE hardware configuration registers
*/
void vdce_hw_setup(vdce_hw_config_t * register_config)
{
/* all devdbg will be removed after UT */
int status;
dev_dbg(vdce_device, " vdce_hw_setup E\n");
/* setting the hardware register GE ctrl */
regw(register_config->vdce_ctrl, VDCE_CTRL);
dev_dbg(vdce_device, "GE CTRL : %x regr = %x \n",
register_config->vdce_ctrl, regr(VDCE_CTRL));
regw(register_config->vdce_emulation_ctrl, VDCE_EMULATION_CTRL);
dev_dbg(vdce_device, "VDCE_EMULATION_CTRL %x regr = %x\n",
register_config->vdce_emulation_ctrl,
regr(VDCE_EMULATION_CTRL));
/* setting the hardware register sdr_fmt */
regw(register_config->vdce_sdr_fmt, VDCE_SDR_FMT);
dev_dbg(vdce_device, "VDCE_SDR_FMT %x regr = %x\n",
register_config->vdce_sdr_fmt, regr(VDCE_SDR_FMT));
/* setting the hardware register req_sz */
regw(register_config->vdce_req_sz, VDCE_REQ_SZ);
dev_dbg(vdce_device, "VDCE_REQ_SZ %x regr = %x\n",
register_config->vdce_req_sz, regr(VDCE_REQ_SZ));
regw(register_config->vdce_prcs_unit_size, VDCE_PRCS_UNIT_SIZE);
dev_dbg(vdce_device, "VDCE_PRCS_UNIT_SIZE : %x regr = %x \n",
register_config->vdce_prcs_unit_size,
regr(VDCE_PRCS_UNIT_SIZE));
regw(register_config->src_Y_strt_ps, SRC_Y_STRT_PS);
dev_dbg(vdce_device, "SRC_Y_STRT_PS : %x regr = %x \n",
register_config->src_Y_strt_ps, regr(SRC_Y_STRT_PS));
regw(register_config->src_Y_sz, SRC_Y_SZ);
dev_dbg(vdce_device, "SRC_Y_SZ : %x regr = %x \n",
register_config->src_Y_sz, regr(SRC_Y_SZ));
regw(register_config->src_C_strt_ps, SRC_C_STRT_PS);
dev_dbg(vdce_device, "SRC_C_STRT_PS : %x regr = %x \n",
register_config->src_C_strt_ps, regr(SRC_C_STRT_PS));
regw(register_config->src_C_sz, SRC_C_SZ);
dev_dbg(vdce_device, "SRC_C_SZ : %x regr = %x \n",
register_config->src_C_sz, regr(SRC_C_SZ));
regw(register_config->src_bmp_strt_ps, SRC_BMP_STRT_PS);
dev_dbg(vdce_device, "SRC_BMP_STRT_PS : %x regr = %x \n",
register_config->src_bmp_strt_ps, regr(SRC_BMP_STRT_PS));
regw(register_config->src_bmp_sz, SRC_BMP_SZ);
dev_dbg(vdce_device, "SRC_BMP_SZ : %x regr = %x \n",
register_config->src_bmp_sz, regr(SRC_BMP_SZ));
regw(register_config->res_Y_strt_ps, RES_Y_STRT_PS);
dev_dbg(vdce_device, "RES_Y_STRT_PS : %x regr = %x \n",
register_config->res_Y_strt_ps, regr(RES_Y_STRT_PS));
regw(register_config->res_Y_sz, RES_Y_SZ);
dev_dbg(vdce_device, "RES_Y_SZ : %x regr = %x \n",
register_config->res_Y_sz, regr(RES_Y_SZ));
regw(register_config->res_C_strt_ps, RES_C_STRT_PS);
dev_dbg(vdce_device, "RES_C_STRT_PS : %x regr = %x \n",
register_config->res_C_strt_ps, regr(RES_C_STRT_PS));
regw(register_config->res_C_sz, RES_C_SZ);
dev_dbg(vdce_device, "RES_C_SZ : %x regr = %x \n",
register_config->res_C_sz, regr(RES_C_SZ));
regw(register_config->res_bmp_strt_ps, RES_BMP_STRT_PS);
dev_dbg(vdce_device, "RES_BMP_STRT_PS : %x regr = %x \n",
register_config->res_bmp_strt_ps, regr(RES_BMP_STRT_PS));
regw(register_config->rsz_mode, RSZ_MODE);
dev_dbg(vdce_device, "RSZ_MODE : %x regr = %x \n",
register_config->rsz_mode, regr(RSZ_MODE));
regw(register_config->rsz_h_mag, RSZ_H_MAG);
dev_dbg(vdce_device, "RSZ_H_MAG : %x regr = %x \n",
register_config->rsz_h_mag, regr(RSZ_H_MAG));
regw(register_config->rsz_v_mag, RSZ_V_MAG);
dev_dbg(vdce_device, "RSZ_V_MAG : %x regr = %x \n",
register_config->rsz_v_mag, regr(RSZ_V_MAG));
regw(register_config->rsz_h_phase, RSZ_H_PHASE);
dev_dbg(vdce_device, "RSZ_H_PHASE : %x regr = %x \n",
register_config->rsz_h_phase, regr(RSZ_H_PHASE));
regw(register_config->rsz_v_phase, RSZ_V_PHASE);
dev_dbg(vdce_device, "RSZ_V_PHASE : %x regr = %x \n",
register_config->rsz_v_phase, regr(RSZ_V_PHASE));
regw(register_config->rsz_alf_intensity, RSZ_ALF_INTENSITY);
dev_dbg(vdce_device, "RSZ_ALF_INTENSITY : %x regr = %x \n",
register_config->rsz_alf_intensity, regr(RSZ_ALF_INTENSITY));
regw(register_config->ccv_mode, CCV_MODE);
dev_dbg(vdce_device, "CCV_MODE : %x regr = %x \n",
register_config->ccv_mode, regr(CCV_MODE));
regw(register_config->bld_lut[0], BLD_LUT_00);
dev_dbg(vdce_device, "BLD_LUT_00 : %x regr = %x \n",
register_config->bld_lut[0], regr(BLD_LUT_00));
regw(register_config->bld_lut[1], BLD_LUT_01);
dev_dbg(vdce_device, "BLD_LUT_01 : %x regr = %x \n",
register_config->bld_lut[1], regr(BLD_LUT_01));
regw(register_config->bld_lut[2], BLD_LUT_02);
dev_dbg(vdce_device, "BLD_LUT_02 : %x regr = %x \n",
register_config->bld_lut[2], regr(BLD_LUT_02));
regw(register_config->bld_lut[3], BLD_LUT_03);
dev_dbg(vdce_device, "BLD_LUT_03 : %x regr = %x \n",
register_config->bld_lut[3], regr(BLD_LUT_03));
regw(register_config->rgmp_ctrl, RGMP_CTRL);
dev_dbg(vdce_device, "RGMP_CTRL : %x regr = %x \n",
register_config->rgmp_ctrl, regr(RGMP_CTRL));
regw(register_config->epd_luma_width, EPD_LUMA_WIDTH);
dev_dbg(vdce_device, "EPD_LUMA_WIDTH : %x regr = %x \n",
register_config->epd_luma_width, regr(EPD_LUMA_WIDTH));
regw(register_config->epd_chroma_width, EPD_CHROMA_WIDTH);
dev_dbg(vdce_device, "EPD_CHROMA_WIDTH : %x regr = %x \n",
register_config->epd_chroma_width, regr(EPD_CHROMA_WIDTH));
/* source addres for luma and chroma */
regw(register_config->vdce_src_strt_add_ytop, VDCE_SRC_STRT_ADD_YTOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_YTOP %x regr = %x\n",
register_config->vdce_src_strt_add_ytop,
regr(VDCE_SRC_STRT_ADD_YTOP));
regw(register_config->vdce_src_strt_add_ctop, VDCE_SRC_STRT_ADD_CTOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_CTOP %x regr = %x\n",
register_config->vdce_src_strt_add_ctop,
regr(VDCE_SRC_STRT_ADD_CTOP));
regw(register_config->vdce_src_strt_add_ybot, VDCE_SRC_STRT_ADD_YBOT);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_YBOT %x regr = %x\n",
register_config->vdce_src_strt_add_ybot,
regr(VDCE_SRC_STRT_ADD_YBOT));
regw(register_config->vdce_src_strt_add_cbot, VDCE_SRC_STRT_ADD_CBOT);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_CBOT %x regr = %x\n",
register_config->vdce_src_strt_add_cbot,
regr(VDCE_SRC_STRT_ADD_CBOT));
/* result address for luma and chroma */
regw(register_config->vdce_res_strt_add_ytop, VDCE_RES_STRT_ADD_YTOP);
dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_YTOP %x regr = %x\n",
register_config->vdce_res_strt_add_ytop,
regr(VDCE_RES_STRT_ADD_YTOP));
regw(register_config->vdce_res_strt_add_ctop, VDCE_RES_STRT_ADD_CTOP);
dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_CTOP %x regr = %x\n",
register_config->vdce_res_strt_add_ctop,
regr(VDCE_RES_STRT_ADD_CTOP));
regw(register_config->vdce_res_strt_add_ybot, VDCE_RES_STRT_ADD_YBOT);
dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_YTOP %x regr = %x\n",
register_config->vdce_res_strt_add_ybot,
regr(VDCE_RES_STRT_ADD_YBOT));
regw(register_config->vdce_res_strt_add_cbot, VDCE_RES_STRT_ADD_CBOT);
dev_dbg(vdce_device, "VDCE_RES_STRT_ADD_CBOT %x regr = %x\n",
register_config->vdce_res_strt_add_cbot,
regr(VDCE_RES_STRT_ADD_CBOT));
/* source offset for luma and chroma */
regw(register_config->vdce_src_add_ofst_ytop, VDCE_SRC_STRT_OFF_YTOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_YTOP %x regr = %x\n",
register_config->vdce_src_add_ofst_ytop,
regr(VDCE_SRC_STRT_OFF_YTOP));
regw(register_config->vdce_src_add_ofst_ctop, VDCE_SRC_STRT_OFF_CTOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_CTOP %x regr = %x\n",
register_config->vdce_src_add_ofst_ctop,
regr(VDCE_SRC_STRT_OFF_CTOP));
regw(register_config->vdce_src_add_ofst_ybot, VDCE_SRC_STRT_OFF_YBOT);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_YBOT %x regr = %x\n",
register_config->vdce_src_add_ofst_ybot,
regr(VDCE_SRC_STRT_OFF_YBOT));
regw(register_config->vdce_src_add_ofst_cbot, VDCE_SRC_STRT_OFF_CBOT);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_CBOT %x regr = %x\n",
register_config->vdce_src_add_ofst_cbot,
regr(VDCE_SRC_STRT_OFF_CBOT));
/* result offset for luma and chroma */
regw(register_config->vdce_res_strt_off_ytop, VDCE_RES_STRT_OFF_YTOP);
dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_YTOP %x regr = %x\n",
register_config->vdce_res_strt_off_ytop,
regr(VDCE_RES_STRT_OFF_YTOP));
regw(register_config->vdce_res_strt_off_ctop, VDCE_RES_STRT_OFF_CTOP);
dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_CTOP %x regr = %x\n",
register_config->vdce_res_strt_off_ctop,
regr(VDCE_RES_STRT_OFF_CTOP));
regw(register_config->vdce_res_strt_off_ybot, VDCE_RES_STRT_OFF_YBOT);
dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_YBOT %x regr = %x\n",
register_config->vdce_res_strt_off_ybot,
regr(VDCE_RES_STRT_OFF_YBOT));
regw(register_config->vdce_res_strt_off_cbot, VDCE_RES_STRT_OFF_CBOT);
dev_dbg(vdce_device, "VDCE_RES_STRT_OFF_CBOT %x regr = %x\n",
register_config->vdce_res_strt_off_cbot,
regr(VDCE_RES_STRT_OFF_CBOT));
/* bitmap address and offset for luma and chroma */
regw(register_config->vdce_src_strt_add_bmp_top,
VDCE_SRC_STRT_ADD_BMP_TOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_BMP_TOP %x regr = %x\n",
register_config->vdce_src_strt_add_bmp_top,
regr(VDCE_SRC_STRT_ADD_BMP_TOP));
regw(register_config->vdce_src_strt_add_bmp_bot,
VDCE_SRC_STRT_ADD_BMP_BOT);
dev_dbg(vdce_device, "VDCE_SRC_STRT_ADD_BMP_BOT %x regr = %x\n",
register_config->vdce_src_strt_add_bmp_bot,
regr(VDCE_SRC_STRT_ADD_BMP_BOT));
regw(register_config->vdce_src_strt_off_bmp_top,
VDCE_SRC_STRT_OFF_BMP_TOP);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_BMP_TOP %x regr = %x\n",
register_config->vdce_src_strt_off_bmp_top,
regr(VDCE_SRC_STRT_OFF_BMP_TOP));
regw(register_config->vdce_src_strt_off_bmp_bot,
VDCE_SRC_STRT_OFF_BMP_BOT);
status = regr(VDCE_STATUS);
dev_dbg(vdce_device, "VDCE_SRC_STRT_OFF_BMP_BOT %x regr = %x\n",
register_config->vdce_src_strt_off_bmp_bot,
regr(VDCE_SRC_STRT_OFF_BMP_BOT));
dev_dbg(vdce_device, "vdce_hw_setup L\n");
}
static void*
dp8390write(Dp8390* ctlr, ulong to, void* from, ulong len)
{
ulong crda;
uchar cr;
int timo, width;
top:
/*
* Write some data to offset 'to' in the card's memory
* using the DP8390 remote DMA facility, reading it at
* 'from' in main memory, via the I/O data port.
*/
cr = regr(ctlr, Cr) & ~Txp;
regw(ctlr, Cr, Page0|RdABORT|Sta);
regw(ctlr, Isr, Rdc);
len = ROUNDUP(len, ctlr->width);
/*
* Set up the remote DMA address and count.
* This is straight from the DP8390[12D] datasheet,
* hence the initial set up for read.
* Assumption here that the A7000 EtherV card will
* never need a dummyrr.
*/
if(ctlr->dummyrr && (ctlr->width == 1 || ctlr->width == 2)){
if(ctlr->width == 2)
width = 1;
else
width = 0;
crda = to-1-width;
regw(ctlr, Rbcr0, (len+1+width) & 0xFF);
regw(ctlr, Rbcr1, ((len+1+width)>>8) & 0xFF);
regw(ctlr, Rsar0, crda & 0xFF);
regw(ctlr, Rsar1, (crda>>8) & 0xFF);
regw(ctlr, Cr, Page0|RdREAD|Sta);
for(timo=0;; timo++){
if(timo > 10000){
print("ether8390: dummyrr timeout; assuming nodummyrr\n");
ctlr->dummyrr = 0;
goto top;
}
crda = regr(ctlr, Crda0);
crda |= regr(ctlr, Crda1)<<8;
if(crda == to){
/*
* Start the remote DMA write and make sure
* the registers are correct.
*/
regw(ctlr, Cr, Page0|RdWRITE|Sta);
crda = regr(ctlr, Crda0);
crda |= regr(ctlr, Crda1)<<8;
if(crda != to)
panic("crda write %lud to %lud", crda, to);
break;
}
}
}
else{
/*
* vdce_clear_status : Function to clear the status
*/
inline int vdce_clear_status(void)
{
regw(1, VDCE_STATUS_CLR);
return 0;
}
void
main(void)
{
regw(TxFrame, 0x1234);
}
