void arm64_release(void* ctx) { TCGContext *s = (TCGContext *) ctx; g_free(s->tb_ctx.tbs); struct uc_struct* uc = s->uc; ARMCPU* cpu = (ARMCPU*) uc->cpu; g_free(cpu->cpreg_indexes); g_free(cpu->cpreg_values); g_free(cpu->cpreg_vmstate_indexes); g_free(cpu->cpreg_vmstate_values); release_common(ctx); }
void m68k_release(void* ctx) { release_common(ctx); TCGContext *tcg_ctx = (TCGContext *) ctx; g_free(tcg_ctx->tb_ctx.tbs); g_free(tcg_ctx->QREG_PC); g_free(tcg_ctx->QREG_SR); g_free(tcg_ctx->QREG_CC_OP); g_free(tcg_ctx->QREG_CC_DEST); g_free(tcg_ctx->QREG_CC_SRC); g_free(tcg_ctx->QREG_CC_X); g_free(tcg_ctx->QREG_DIV1); g_free(tcg_ctx->QREG_DIV2); g_free(tcg_ctx->QREG_MACSR); g_free(tcg_ctx->QREG_MAC_MASK); int i; for (i = 0; i < 8; i++) { g_free(tcg_ctx->cpu_dregs[i]); g_free(tcg_ctx->cpu_aregs[i]); } g_free(tcg_ctx->NULL_QREG); g_free(tcg_ctx->store_dummy); }
void x86_release(void *ctx) { release_common(ctx); TCGContext *s = (TCGContext *) ctx; // arch specific g_free(s->cpu_A0); g_free(s->cpu_T[0]); g_free(s->cpu_T[1]); g_free(s->cpu_tmp0); g_free(s->cpu_tmp4); g_free(s->cpu_cc_srcT); g_free(s->cpu_cc_dst); g_free(s->cpu_cc_src); g_free(s->cpu_cc_src2); int i; for (i = 0; i < CPU_NB_REGS; ++i) { g_free(s->cpu_regs[i]); } g_free(s->tb_ctx.tbs); }