static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; unsigned long bmbound_hi; unsigned long smmrrh; unsigned long smmrrl; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); int index = 0; /* Read standard PCI resources. */ pci_dev_read_resources(dev); /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ base_k = RES_IN_KiB(0); size_k = RES_IN_KiB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); /* The SMMRR registers are 1MiB granularity with smmrrh being * inclusive of the SMM region. */ smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; /* 0xc0000 -> smrrl - cacheable and usable */ base_k = RES_IN_KiB(0xc0000); size_k = smmrrl - base_k; ram_resource(dev, index++, base_k, size_k); if (smmrrh > smmrrl) reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); /* All address space between bmbound and smmrrh is unusable. */ bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); /* The BMBOUND_HI register matches register bits of 31:24 with address * bits of 35:28. Therefore, shift register to align properly. */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); if (CONFIG(CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); }
static void nc_read_resources(struct device *dev) { unsigned long base_k; int index = 0; unsigned long size_k; /* Read standard PCI resources. */ pci_dev_read_resources(dev); /* 0 -> 0xa0000 */ base_k = 0; size_k = 0xa0000 - base_k; ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xdffff: RAM * 0xe0000 - 0xfffff: ROM shadow */ base_k += size_k; size_k = 0xc0000 - base_k; mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); base_k += size_k; size_k = 0x100000 - base_k; reserved_ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* 0x100000 -> cbmem_top - cacheable and usable */ base_k += size_k; size_k = (unsigned long)cbmem_top() - base_k; ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* cbmem_top -> 0xc0000000 - reserved */ base_k += size_k; size_k = 0xc0000000 - base_k; reserved_ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); /* 0xc0000000 -> 4GiB is mmio. */ base_k += size_k; size_k = 0x100000000ull - base_k; mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); }
void chromeos_reserve_ram_oops(struct device *dev, int idx) { const unsigned long base = ramoops_base >> 10; const unsigned long size = ramoops_size >> 10; reserved_ram_resource(dev, idx, base, size); boot_state_sched_on_exit(&bscb_ramoops, BS_WRITE_TABLES); }
static void soc_read_resources(device_t dev) { unsigned long index = 0; int i; uintptr_t begin, end; size_t size; for (i = 0; i < CARVEOUT_NUM; i++) { carveout_range(i, &begin, &size); if (size == 0) continue; reserved_ram_resource(dev, index++, begin * KiB, size * KiB); } memory_in_range_below_4gb(&begin, &end); size = end - begin; ram_resource(dev, index++, begin * KiB, size * KiB); memory_in_range_above_4gb(&begin, &end); size = end - begin; ram_resource(dev, index++, begin * KiB, size * KiB); }
static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, DRAMSIZE4GB / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, _dram_reserved_size / KiB); }