void ETH1_init(u8_t *mac_addr)
{
outpw(REG_CLK_HCLKEN, inpw(REG_CLK_HCLKEN) | (1 << 17)); // EMAC1 clk
outpw(REG_CLK_DIVCTL8, (inpw(REG_CLK_DIVCTL8) & ~0xFF) | 0xA0); // MDC clk divider
// Multi function pin setting
outpw(REG_SYS_GPE_MFPL, (inpw(REG_SYS_GPE_MFPL) & ~0xFFFFFF00) | 0x11111100);
outpw(REG_SYS_GPE_MFPH, (inpw(REG_SYS_GPE_MFPH) & ~0xFFFF) | 0x1111);
// Reset MAC
outpw(REG_EMAC1_MCMDR, 0x1000000);
init_tx_desc();
init_rx_desc();
set_mac_addr(mac_addr); // need to reconfigure hardware address 'cos we just RESET emc...
reset_phy();
outpw(REG_EMAC1_MCMDR, inpw(REG_EMAC1_MCMDR) | 0x121); // strip CRC, TX on, Rx on
outpw(REG_EMAC1_MIEN, inpw(REG_EMAC1_MIEN) | 0x01250C11); // Except tx/rx ok, enable rdu, txabt, tx/rx bus error.
sysInstallISR(IRQ_LEVEL_1, EMC1_TX_IRQn, (PVOID)ETH1_TX_IRQHandler);
sysInstallISR(IRQ_LEVEL_1, EMC1_RX_IRQn, (PVOID)ETH1_RX_IRQHandler);
sysEnableInterrupt(EMC1_TX_IRQn);
sysEnableInterrupt(EMC1_RX_IRQn);
ETH1_TRIGGER_RX();
sysSetTimerEvent(TIMER0, 200, (PVOID)chk_link); // check link status every 2 sec
}
int reset_phy_r(void)
{
#ifdef DEBUG
puts("Reset Ethernet PHY\n");
#endif
reset_phy();
return 0;
}
static int initr_net(void)
{
puts("Net: ");
eth_initialize();
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_MXC_SPI
setup_iomux_spi();
power_init();
#endif
reset_phy();
#ifdef CONFIG_HW_WATCHDOG
if(1){
/* NOTE: */
/* hw_watchdog_init() seems not work, use the following code */
/* which is stolen from linux kerenel to init the watchdog. */
/* hw_watchdog_reset() works fine! */
#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
u16 val = readw(WDOG1_BASE_ADDR);
/* Strip the old watchdog Time-Out value */
val &= ~IMX2_WDT_WCR_WT;
/* Generate reset if WDOG times out */
val &= ~IMX2_WDT_WCR_WRE;
/* Keep Watchdog Disabled */
val &= ~IMX2_WDT_WCR_WDE;
/* Set the watchdog's Time-Out value */
val |= WDOG_SEC_TO_COUNT(CONFIG_WATCHDOG_TIMEOUT_MSECS/1000);
writew(val, WDOG1_BASE_ADDR);
/* enable the watchdog */
val |= IMX2_WDT_WCR_WDE;
writew(val, WDOG1_BASE_ADDR);
/* According to i,MX515 Reference Manual, the PDE bit */
/* should be cleared within 16 second after boot */
/* Write to the PDE (Power Down Enable) bit */
writew(0, WDOG1_BASE_ADDR+8);
#undef IMX2_WDT_WCR_WT
#undef IMX2_WDT_WCR_WRE
#undef IMX2_WDT_WCR_WDE
#undef WDOG_SEC_TO_COUNT
}
#endif
return 0;
}
/*-------------------------------------------------------------------------
* Start the TI USBHOST controller
*/
static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
{
dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
reset_phy(omap);
/* Enable USB clocks */
if(enable_omap_clocks(omap,1) != 0)
goto end_error;
/* TLL config */
if(setup_tll(omap) != 0){
enable_omap_clocks(omap,0);
goto end_error;
}
/* UHH config */
if(set_uhh_mode(omap) != 0){
enable_omap_clocks(omap,0);
goto end_error;
}
goto end_ok;
end_error:
if (omap->phy_reset) {
if (gpio_is_valid(omap->reset_gpio_port[0]))
gpio_free(omap->reset_gpio_port[0]);
if (gpio_is_valid(omap->reset_gpio_port[1]))
gpio_free(omap->reset_gpio_port[1]);
}
return -1;
end_ok:
if (omap->phy_reset) {
/* Refer ISSUE1:
* Hold the PHY in RESET for enough time till
* PHY is settled and ready
*/
udelay(100);
if (gpio_is_valid(omap->reset_gpio_port[0]))
gpio_set_value(omap->reset_gpio_port[0], 0);
if (gpio_is_valid(omap->reset_gpio_port[1]))
gpio_set_value(omap->reset_gpio_port[1], 0);
}
return 0;
}
int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
pci->peer &= 0xffffffdf; /* disable master abort */
#endif
/* Why is the phy reset done _after_ the ethernet
* initialization in arch/ppc/lib/board.c?
* Do it here so it's done before the TSECs are used.
*/
reset_phy();
return 0;
}
static void chk_link(void)
{
unsigned int reg;
reg = mdio_read(CONFIG_PHY_ADDR, MII_BMSR);
if (reg & BMSR_LSTATUS) {
if (!plugged) {
plugged = 1;
reset_phy();
outpw(REG_EMAC0_MCMDR, inpw(REG_EMAC0_MCMDR) | 0x101);
}
} else {
if (plugged) {
plugged = 0;
outpw(REG_EMAC0_MCMDR, inpw(REG_EMAC0_MCMDR) & ~0x101);
}
}
}
void start_armboot (void)
{
init_fnc_t **init_fnc_ptr;
char *s;
int mmc_exist = 0;
#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
unsigned long addr;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset ((void*)gd, 0, sizeof (gd_t));
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
memset (gd->bd, 0, sizeof (bd_t));
// gd->flags |= GD_FLG_RELOC;
monitor_flash_len = _bss_start - _armboot_start;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
/* armboot_start is defined in the board-specific linker script */
mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
display_flash_config (flash_init ());
#endif /* CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_VFD
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for VFD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
vfd_setmem (addr);
gd->fb_base = addr;
#endif /* CONFIG_VFD */
#ifdef CONFIG_LCD
/* board init may have inited fb_base */
if (!gd->fb_base) {
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for LCD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
lcd_setmem (addr);
gd->fb_base = addr;
}
#endif /* CONFIG_LCD */
#if defined(CONFIG_CMD_NAND)
puts ("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts ("MMC: ");
mmc_exist = mmc_initialize (gd->bd);
if (mmc_exist != 0)
{
puts ("0 MB\n");
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
env_relocate ();
#ifdef CONFIG_VFD
/* must do this after the framebuffer is allocated */
drv_vfd_init();
#endif /* CONFIG_VFD */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
stdio_init (); /* get the devices list going. */
jumptable_init ();
#if defined(CONFIG_API)
/* Initialize API */
api_init ();
#endif
console_init_r (); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init ();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r ();
#endif
/* enable exceptions */
enable_interrupts ();
/* Perform network card initialisation if necessary */
#ifdef CONFIG_DRIVER_TI_EMAC
/* XXX: this needs to be moved to board init */
extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
if (getenv ("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
davinci_eth_set_mac_addr(enetaddr);
}
#endif
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv ("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
}
#if defined(CONFIG_CMD_NET)
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
}
#endif
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug ("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop ();
}
/* NOTREACHED - no way out of command loop except booting */
}
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
bd_t *bd;
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
gd = id;
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _end_ofs;
/*
* Enable D$:
* I$, if needed, must be already enabled in start.S
*/
dcache_enable();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv("flashchecksum");
if (s && (*s == 'y')) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
env_relocate();
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
s = getenv("loadaddr");
if (s != NULL)
load_addr = simple_strtoul(s, NULL, 16);
#if defined(CONFIG_CMD_NET)
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
#ifdef BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram;
uchar memsz[32];
#ifdef CONFIG_PRAM
char *s;
s = getenv("pram");
if (s != NULL)
pram = simple_strtoul(s, NULL, 10);
else
pram = CONFIG_PRAM;
#else
pram = 0;
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
/*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
* data can be written, BSS has been cleared, the stack size in not
* that critical any more, etc.
*/
void board_init_r(gd_t *id, ulong dest_addr)
{
bd_t *bd;
ulong malloc_start;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
gd = id; /* initialize RAM version of global data */
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
* The gd->arch.cpu pointer is set to an address in flash before
* relocation. We need to update it to point to the same CPU entry
* in RAM.
*/
gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
/*
* If we didn't know the cpu mask & # cores, we can save them of
* now rather than 'computing' them constantly
*/
fixup_cpu();
#endif
#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
/*
* Some systems need to relocate the env_addr pointer early because the
* location it points to will get invalidated before env_relocate is
* called. One example is on systems that might use a L2 or L3 cache
* in SRAM mode and initialize that cache from SRAM mode back to being
* a cache in cpu_init_r.
*/
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
serial_initialize();
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
WATCHDOG_RESET();
/*
* Setup trap handlers
*/
trap_init(dest_addr);
#ifdef CONFIG_ADDR_MAP
init_addr_map();
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_R)
board_early_init_r();
#endif
monitor_flash_len = (ulong)&__init_end - dest_addr;
WATCHDOG_RESET();
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
WATCHDOG_RESET();
#if defined(CONFIG_SYS_DELAYED_ICACHE)
icache_enable(); /* it's time to enable the instruction cache */
#endif
#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do early PCI configuration _before_ the flash gets initialised,
* because PCU ressources are crucial for flash access on some boards.
*/
pci_init();
#endif
#if defined(CONFIG_WINBOND_83C553)
/*
* Initialise the ISA bridge
*/
initialise_w83c553f();
#endif
asm("sync ; isync");
mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
if (board_flash_wp_on()) {
printf("Uninitialized - Write Protect On\n");
/* Since WP is on, we can't find real size. Set to 0 */
flash_size = 0;
} else if ((flash_size = flash_init()) > 0) {
#ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X",
crc32(0,
(const unsigned char *)
CONFIG_SYS_FLASH_BASE, flash_size)
);
}
putc('\n');
#else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
#endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
/* update start of FLASH memory */
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
/* size of FLASH memory (final value) */
bd->bi_flashsize = flash_size;
#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
/* Make a update of the Memctrl. */
update_flash_size(flash_size);
#endif
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
/* flash mapped at end of memory map */
bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
#endif
#endif /* !CONFIG_SYS_NO_FLASH */
WATCHDOG_RESET();
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r();
WATCHDOG_RESET();
#ifdef CONFIG_SPI
#if !defined(CONFIG_ENV_IS_IN_EEPROM)
spi_init_f();
#endif
spi_init_r();
#endif
#if defined(CONFIG_CMD_NAND)
WATCHDOG_RESET();
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#ifdef CONFIG_GENERIC_MMC
/*
* MMC initialization is called before relocating env.
* Thus It is required that operations like pin multiplexer
* be put in board_init.
*/
WATCHDOG_RESET();
puts("MMC: ");
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
env_relocate();
/*
* after non-volatile devices & environment is setup and cpu code have
* another round to deal with any initialization that might require
* full access to the environment or loading of some image (firmware)
* from a non-volatile device
*/
cpu_secondary_init_r();
/*
* Fill in missing fields of bd_info.
* We do this here, where we have "normal" access to the
* environment; we used to do this still running from ROM,
* where had to use getenv_f(), which can be pretty slow when
* the environment is in EEPROM.
*/
#if defined(CONFIG_SYS_EXTBDINFO)
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_I2CFAST)
/*
* set bi_iic_fast for linux taking environment variable
* "i2cfast" into account
*/
{
if (getenv_yesno("i2cfast") == 1) {
bd->bi_iic_fast[0] = 1;
bd->bi_iic_fast[1] = 1;
}
}
#endif /* CONFIG_I2CFAST */
#endif /* CONFIG_405GP, CONFIG_405EP */
#endif /* CONFIG_SYS_EXTBDINFO */
#if defined(CONFIG_SC3)
sc3_read_eeprom();
#endif
#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
mac_read_from_eeprom();
#endif
#ifdef CONFIG_CMD_NET
/* kept around for legacy kernels only ... ignore the next section */
eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
#ifdef CONFIG_HAS_ETH1
eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
#endif
#ifdef CONFIG_HAS_ETH2
eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
#endif
#ifdef CONFIG_HAS_ETH3
eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
#endif
#ifdef CONFIG_HAS_ETH4
eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
#endif
#ifdef CONFIG_HAS_ETH5
eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
#endif
#endif /* CONFIG_CMD_NET */
WATCHDOG_RESET();
#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
/*
* Do pci configuration
*/
pci_init();
#endif
/** leave this here (after malloc(), environment and PCI are working) **/
/* Initialize stdio devices */
stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
kgdb_init();
#endif
debug("U-Boot relocated to %08lx\n", dest_addr);
/*
* Enable Interrupts
*/
interrupt_init();
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
WATCHDOG_RESET();
#if defined(CONFIG_CMD_SCSI)
WATCHDOG_RESET();
puts("SCSI: ");
scsi_init();
#endif
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET();
puts("DOC: ");
doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
puts("Net: ");
eth_initialize(bd);
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
WATCHDOG_RESET();
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_CMD_PCMCIA) \
&& !defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts("PCMCIA:");
pcmcia_init();
#endif
#if defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
#ifdef CONFIG_IDE_8xx_PCCARD
puts("PCMCIA:");
#else
puts("IDE: ");
#endif
#if defined(CONFIG_START_IDE)
if (board_start_ide())
ide_init();
#else
ide_init();
#endif
#endif
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
last_stage_init();
#endif
#if defined(CONFIG_CMD_BEDBUG)
WATCHDOG_RESET();
bedbug_init();
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
char memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf(memsz, "%ldk", (ulong) (bd->bi_memsize / 1024) - pram);
setenv("mem", memsz);
}
#endif
#ifdef CONFIG_PS2KBD
puts("PS/2: ");
kbd_init();
#endif
/* Initialization complete - start the monitor */
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
WATCHDOG_RESET();
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
static int scc_init (struct eth_device *dev, bd_t * bis)
{
int i;
scc_enet_t *pram_ptr;
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if defined(CONFIG_LWMON)
reset_phy();
#endif
#ifdef CONFIG_FADS
#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#else
*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif
#endif
pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
rxIdx = 0;
txIdx = 0;
if (!rtx) {
#ifdef CONFIG_SYS_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
dpram_alloc_align (sizeof (RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif
}
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
/* Configure port A pins for Txd and Rxd.
*/
immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
/* Configure port B pins for Txd and Rxd.
*/
immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
#else
#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
#endif
#if defined(PC_ENET_LBK)
/* Configure port C pins to disable External Loopback
*/
immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
#endif /* PC_ENET_LBK */
/* Configure port C pins to enable CLSN and RENA.
*/
immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
/* Configure port A for TCLK and RCLK.
*/
immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
/*
* Configure Serial Interface clock routing -- see section 16.7.5.3
* First, clear all SCC bits to zero, then set the ones we want.
*/
immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
/*
* Initialize SDCR -- see section 16.9.23.7
* SDMA configuration register
*/
immr->im_siu_conf.sc_sdcr = 0x01;
/*
* Setup SCC Ethernet Parameter RAM
*/
pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
rtx->rxbd[i].cbd_datlen = 0; /* Reset */
rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
rtx->txbd[i].cbd_sc =
(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
rtx->txbd[i].cbd_datlen = 0; /* Reset */
rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/*
* Enter Command: Initialize Rx Params for SCC
*/
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr =
((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/*
* Ethernet Specific Parameter RAM
* see table 13-16, pg. 660,
* pg. 681 (example with suggested settings)
*/
pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
#define ea eth_get_dev()->enetaddr
pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
#undef ea
pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
/*
* Enter Command: Initialize Tx Params for SCC
*/
do { /* Spin until ready to issue command */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/* Issue command */
immr->im_cpm.cp_cpcr =
((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
/*
* Mask all Events in SCCM - we use polling mode
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
/*
* Clear Events in SCCE -- Clear bits by writing 1's
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
/*
* Initialize GSMR High 32-Bits
* Settings: Normal Mode
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
/*
* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
* Settings:
* TCI = Invert
* TPL = 48 bits
* TPP = Repeating 10's
* MODE = Ethernet
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
SCC_GSMRL_TPL_48 |
SCC_GSMRL_TPP_10 |
SCC_GSMRL_MODE_ENET);
/*
* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
/*
* Initialize the PSMR
* Settings:
* CRC = 32-Bit CCITT
* NIB = Begin searching for SFD 22 bits after RENA
* FDE = Full Duplex Enable
* LPB = Loopback Enable (Needed when FDE is set)
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
SCC_PSMR_NIB22 |
#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
SCC_PSMR_FDE | SCC_PSMR_LPB |
#endif
#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
SCC_PSMR_BRO |
#endif
#if defined(CONFIG_SCC_ENET_PROMISCOUS)
SCC_PSMR_PRO |
#endif
0;
/*
* Configure Ethernet TENA Signal
*/
#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
#else
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
/*
* Port C is used to control the PHY,MC68160.
*/
immr->im_ioport.iop_pcdir |=
(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* MPC860ADS */
#if defined(CONFIG_AMX860)
/*
* Port B is used to control the PHY,MC68160.
*/
immr->im_cpm.cp_pbdir |=
(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
#endif /* AMX860 */
#ifdef CONFIG_RPXCLASSIC
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
#endif
#ifdef CONFIG_RPXLITE
*((uchar *) BCSR0) |= BCSR0_ETHEN;
#endif
#if defined(CONFIG_QS860T)
/*
* PB27=FDE-, set output low for full duplex
* PB26=Link Test Enable, normally high output
*/
immr->im_cpm.cp_pbdir |= 0x00000030;
immr->im_cpm.cp_pbdat |= 0x00000020;
immr->im_cpm.cp_pbdat &= ~0x00000010;
#endif /* QS860T */
#ifdef CONFIG_MBX
board_ether_init ();
#endif
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_ioport.iop_padir |= PA_ENET_PDN;
immr->im_ioport.iop_padat |= PA_ENET_PDN;
#elif defined(PB_ENET_PDN)
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
#elif defined(PC_ENET_PDN)
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
#elif defined(PD_ENET_PDN)
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
#endif
#endif
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/*
* Work around transmit problem with first eth packet
*/
#if defined (CONFIG_FADS)
udelay (10000); /* wait 10 ms */
#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
udelay (100000); /* wait 100 ms */
#endif
return 1;
}
/*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
* data can be written, BSS has been cleared, the stack size in not
* that critical any more, etc.
*/
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
bd_t *bd;
ulong malloc_start;
extern void malloc_bin_reloc(void);
gd = id;
bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = &_end - &_start;
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
malloc_bin_reloc();
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
gd->bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
gd->bd->bi_flashsize = flash_init();
gd->bd->bi_flashoffset = CONFIG_SYS_FLASH_BASE + gd->bd->bi_flashsize;
if (gd->bd->bi_flashsize)
display_flash_config(gd->bd->bi_flashsize);
#endif /* CONFIG_SYS_NO_FLASH */
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_IDE)
puts("IDE: ");
ide_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
/* initialize environment */
env_relocate();
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
nds32_pci_init();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
#if defined(CONFIG_USE_IRQ)
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
#endif
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
#ifdef BOARD_LATE_INIT
board_late_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;)
main_loop();
/* NOTREACHED - no way out of command loop except booting */
}
void board_init_r(gd_t *id, ulong dest_addr)
{
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
/*
* TODO: printing of the clock inforamtion of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
*/
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
serial_initialize();
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
power_init_board();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (getenv_yesno("flashchecksum") == 1) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_CMD_SCSI
puts("SCSI: ");
scsi_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
if (should_load_env())
env_relocate();
else
set_default_env(NULL);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
# ifdef CONFIG_OF_CONTROL
/* Put this here so it appears on the LCD, now it is ready */
display_fdt_model(gd->fdt_blob);
# else
checkboard();
# endif
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_FASTBOOT
fastboot_setup();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
uchar memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
#ifdef CONFIG_FASTBOOT
check_fastboot();
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
/*****************************************
* Routine: ddr_init
* Description: Configure DDR
* EMIF1 -- CS0 -- DDR1 (256 MB)
* EMIF2 -- CS0 -- DDR2 (256 MB)
*****************************************/
void do_ddr_init(const struct ddr_regs *emif1_ddr_regs,
const struct ddr_regs *emif2_ddr_regs)
{
unsigned int rev;
rev = omap_revision();
if (rev == OMAP4430_ES1_0)
{
/* Configure the Control Module DDRIO device */
__raw_writel(0x1c1c1c1c, 0x4A100638);
__raw_writel(0x1c1c1c1c, 0x4A10063c);
__raw_writel(0x1c1c1c1c, 0x4A100640);
__raw_writel(0x1c1c1c1c, 0x4A100648);
__raw_writel(0x1c1c1c1c, 0x4A10064c);
__raw_writel(0x1c1c1c1c, 0x4A100650);
/* LPDDR2IO set to NMOS PTV */
__raw_writel(0x00ffc000, 0x4A100704);
} else if (rev == OMAP4430_ES2_0) {
__raw_writel(0x9e9e9e9e, 0x4A100638);
__raw_writel(0x9e9e9e9e, 0x4A10063c);
__raw_writel(0x9e9e9e9e, 0x4A100640);
__raw_writel(0x9e9e9e9e, 0x4A100648);
__raw_writel(0x9e9e9e9e, 0x4A10064c);
__raw_writel(0x9e9e9e9e, 0x4A100650);
/* LPDDR2IO set to NMOS PTV */
__raw_writel(0x00ffc000, 0x4A100704);
} else if (rev >= OMAP4430_ES2_1) {
__raw_writel(0x7c7c7c7c, 0x4A100638);
__raw_writel(0x7c7c7c7c, 0x4A10063c);
__raw_writel(0x7c787c00, 0x4A100640);
__raw_writel(0x7c7c7c7c, 0x4A100648);
__raw_writel(0x7c7c7c7c, 0x4A10064c);
__raw_writel(0x7c787c00, 0x4A100650);
/*
* Adjust Internal Vref controls to reduce leakage
* for chip retention (Core OSWR)
*/
__raw_writel(0xa388bc03, 0x4A100644);
__raw_writel(0xa388bc03, 0x4A100654);
/* LPDDR2IO set to NMOS PTV */
/* To be updated according to Process */
/*__raw_writel(0x00ffc000, 0x4A100704); */
}
/* DDR needs to be initialised @ 19.2 MHz
* So put core DPLL in bypass mode
* Configure the Core DPLL but don't lock it
*/
configure_core_dpll_no_lock();
/* No IDLE: BUG in SDC */
__raw_writel(0x0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
__raw_writel(0x0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
/* Configure EMIF1 */
emif_config(EMIF1_BASE, emif1_ddr_regs);
/* Configure EMIF2 */
emif_config(EMIF2_BASE, emif2_ddr_regs);
/* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
lock_core_dpll_shadow();
/* TODO: SDC needs few hacks to get DDR freq update working */
/* Set DLL_OVERRIDE = 0 */
__raw_writel(0x0, CM_DLL_CTRL);
spin_delay(200);
/* Check for DDR PHY ready for EMIF1 & EMIF2 */
while(((__raw_readl(EMIF1_BASE + EMIF_STATUS) & 0x04) != 0x04)
|| ((__raw_readl(EMIF2_BASE + EMIF_STATUS) & 0x04) != 0x04));
/* Reprogram the DDR PYHY Control register */
/* PHY control values */
sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
/* Put the Core Subsystem PD to ON State */
/* No IDLE: BUG in SDC */
__raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
__raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
/* SYSTEM BUG:
* In n a specific situation, the OCP interface between the DMM and
* EMIF may hang.
* 1. A TILER port is used to perform 2D burst writes of
* width 1 and height 8
* 2. ELLAn port is used to perform reads
* 3. All accesses are routed to the same EMIF controller
*
* Work around to avoid this issue REG_SYS_THRESH_MAX value should
* be kept higher than default 0x7. As per recommondation 0x0A will
* be used for better performance with REG_LL_THRESH_MAX = 0x00
*/
if (omap_revision() >= OMAP4460_ES1_0) {
__raw_writel(0x0A300000, EMIF1_BASE + EMIF_L3_CONFIG);
__raw_writel(0x0A300000, EMIF2_BASE + EMIF_L3_CONFIG);
} else {
__raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
__raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
}
reset_phy(EMIF1_BASE);
reset_phy(EMIF2_BASE);
}
void board_init_r(gd_t *id, ulong dest_addr)
{
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
gd = id;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
monitor_flash_len = _end_ofs;/*u-boot.lds中定义*/
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects//打印一些版本信息，电源管理信息 */
/*
* TODO: printing of the clock inforamtion of the board is now
* implemented as part of bdinfo command. Currently only support for
* davinci SOC's is added. Remove this check once all the board
* implement this.
*/
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
#ifdef CONFIG_SERIAL_MULTI
#ifndef CONFIG_CPU_EXYNOS5410
serial_initialize();
#endif
#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_ARCH_EARLY_INIT_R
arch_early_init_r();
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
char *s = getenv("flashchecksum");
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
if (s && (*s == 'y')) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#if defined(CONFIG_CMD_NAND)
puts("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_GENERIC_MMC
puts("MMC: ");
mmc_initialize(gd->bd);
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
env_relocate();
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();//晚点执行的初始化在smdk5420.c
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
puts("Net: ");
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram = 0;
uchar memsz[32];
#ifdef CONFIG_PRAM
pram = getenv_ulong("pram", 10, CONFIG_PRAM);
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();//进入命令行模式
}
/* NOTREACHED - no way out of command loop except booting */
}
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
//bd_t *bd;
ulong malloc_start;
#ifdef CONFIG_NONCACHE_MEMORY
uint malloc_noncache_start;
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
int workmode;
int ret;
gd = id;
//bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _end_ofs;
malloc_start = dest_addr - TOTAL_MALLOC_LEN - sizeof(struct spare_boot_head_t);
#ifdef CONFIG_NONCACHE_MEMORY_SIZE
malloc_start &= (~(0x00100000 -1));
malloc_noncache_start = malloc_start - CONFIG_NONCACHE_MEMORY_SIZE;
gd->malloc_noncache_start = malloc_noncache_start;
#endif
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_NONCACHE_MEMORY
mem_noncache_malloc_init(malloc_noncache_start, CONFIG_NONCACHE_MEMORY_SIZE);
#endif
workmode = uboot_spare_head.boot_data.work_mode;
debug("work mode %d\n", workmode);
axp_reinit();
//uboot_spare_head.boot_data.work_mode = WORK_MODE_CARD_PRODUCT;
#ifdef CONFIG_ARCH_HOMELET
gpio_control();
#endif
#if 0
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv("flashchecksum");
if (s && (*s == 'y')) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
sunxi_dma_init();
#ifdef CONFIG_ALLWINNER
#ifdef DEBUG
puts("ready to config storage\n");
#endif
if((workmode == WORK_MODE_BOOT) || (workmode == WORK_MODE_CARD_PRODUCT))
{
#if defined(CONFIG_SUNXI_DISPLAY)
drv_disp_init();
#endif
board_display_device_open();
board_display_layer_request();
}
ret = sunxi_flash_handle_init();
if(!ret)
{
sunxi_partition_init();
}
#else
#if defined(CONFIG_CMD_NAND)
if(!storage_type){
puts("NAND: ");
nand_init(); /* go init the NAND */
}
#endif/*CONFIG_CMD_NAND*/
#if defined(CONFIG_GENERIC_MMC)
if(storage_type){
puts("MMC: ");
mmc_initialize(bd);
}
#endif/*CONFIG_GENERIC_MMC*/
#endif/*CONFIG_ALLWINNER*/
#ifdef CONFIG_ARCH_HOMELET
extern int check_boot_recovery_key();
extern int sprite_form_sysrecovery();
extern int sprite_led_init(void);
extern int sprite_led_exit(int status);
if (!check_boot_recovery_key())
{
sprite_led_init();
ret = sprite_form_sysrecovery();
sprite_led_exit(ret);
}
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
env_relocate();
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
s = getenv("loadaddr");
if (s != NULL)
load_addr = simple_strtoul(s, NULL, 16);
#if defined(CONFIG_CMD_NET)
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
#ifdef BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram;
uchar memsz[32];
#ifdef CONFIG_PRAM
char *s;
s = getenv("pram");
if (s != NULL)
pram = simple_strtoul(s, NULL, 10);
else
pram = CONFIG_PRAM;
#else
pram = 0;
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
//sprite_cartoon_test();
if(workmode == WORK_MODE_BOOT)
{
#if defined(CONFIG_SUNXI_SCRIPT_REINIT)
{
FATFS script_mount;
int ret;
uint read_bytes = 0;
FIL script_fs;
uchar *buf = NULL;
f_mount(0, &script_mount);
ret = f_open (&script_fs, "0:script.bin", FA_OPEN_EXISTING | FA_READ | FA_WRITE );
if(ret)
{
printf("cant open script.bin, maybe it is not exist\n");
}
else
{
buf = (uchar *)malloc(100 * 1024);
memset(buf, 0, 100 * 1024);
if(!f_read(&script_fs, buf, 100 * 1024, &read_bytes))
{
printf("f_read read bytes = %d\n", read_bytes);
}
f_close(&script_fs);
puts("try to unlink file ");
printf("%d\n", f_unlink("0:script.bin"));
}
f_mount(0, NULL);
if(read_bytes > 0)
{
char *tmp_target_buffer = (char *)(CONFIG_SYS_TEXT_BASE - 0x01000000);
sunxi_flash_exit(1);
memcpy(tmp_target_buffer + uboot_spare_head.boot_head.uboot_length, buf, read_bytes);
sunxi_sprite_download_uboot(tmp_target_buffer, uboot_spare_head.boot_data.storage_type, 1);
reset_cpu(0);
}
if(buf)
{
free(buf);
}
}
#endif
printf("WORK_MODE_BOOT\n");
#ifdef CONFIG_ALLWINNER
#if (defined(CONFIG_SUN6I) || defined(CONFIG_A50) || defined(CONFIG_SUN7I))
if(!ret)
{
#ifndef CONFIG_ARCH_HOMELET
printf("board_status_probe\n");
board_status_probe(0);
#endif
printf("sunxi_bmp_display\n");
sunxi_bmp_display("bootlogo.bmp");
}
#endif
printf("WORK_MODE_BOOT\n");
#endif
}
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;)
{
main_loop();
}
hang();
/* NOTREACHED - no way out of command loop except booting */
}
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
ulong size;
static bd_t bd_data;
static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
show_boot_progress(0x21);
/* Global data pointer is now writable */
gd = &gd_data;
memcpy(gd, id, sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
gd->bd = &bd_data;
memset (gd->bd, 0, sizeof (bd_t));
show_boot_progress(0x22);
gd->baudrate = CONFIG_BAUDRATE;
mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
CONFIG_SYS_MALLOC_LEN);
for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0)
hang ();
}
show_boot_progress(0x23);
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
/* configure available FLASH banks */
size = flash_init();
display_flash_config(size);
show_boot_progress(0x24);
show_boot_progress(0x25);
/* initialize environment */
env_relocate ();
show_boot_progress(0x26);
#ifdef CONFIG_CMD_NET
/* IP Address */
bd_data.bi_ip_addr = getenv_IPaddr ("ipaddr");
#endif
#if defined(CONFIG_PCI)
/*
* Do pci configuration
*/
pci_init();
#endif
show_boot_progress(0x27);
stdio_init ();
jumptable_init ();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#ifdef CONFIG_MISC_INIT_R
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts ("PCMCIA:");
pcmcia_init();
#endif
#if defined(CONFIG_CMD_KGDB)
WATCHDOG_RESET();
puts("KGDB: ");
kgdb_init();
#endif
/* enable exceptions */
enable_interrupts();
show_boot_progress(0x28);
#ifdef CONFIG_STATUS_LED
status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
#if defined(CONFIG_CMD_NET)
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
}
#endif
WATCHDOG_RESET();
#if defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts("IDE: ");
ide_init();
#endif
#if defined(CONFIG_CMD_SCSI)
WATCHDOG_RESET();
puts("SCSI: ");
scsi_init();
#endif
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET();
puts("DOC: ");
doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
puts("Net: ");
eth_initialize(gd->bd);
#endif
#if ( defined(CONFIG_CMD_NET)) && (0)
WATCHDOG_RESET();
# ifdef DEBUG
puts ("Reset Ethernet PHY\n");
# endif
reset_phy();
#endif
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
last_stage_init();
#endif
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif
show_boot_progress(0x29);
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop();
}
/* NOTREACHED - no way out of command loop except booting */
}
/*
************************************************************************
*
* This is the next part if the initialization sequence: we are now
* running from RAM and have a "normal" C environment, i. e. global
* data can be written, BSS has been cleared, the stack size in not
* that critical any more, etc.
*
************************************************************************
*/
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
//bd_t *bd;
ulong malloc_start;
#ifdef CONFIG_NONCACHE_MEMORY
uint malloc_noncache_start;
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
int workmode;
int ret;
#ifdef CONFIG_SUNXI_HDCP_IN_SECURESTORAGE
int hdcpkey_enable=0;
#endif
char storage_type_buf[24] = {0};
char boot_mmc_buf[24] = {0};
gd = id;
//bd = gd->bd;
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _end_ofs;
malloc_start = dest_addr - TOTAL_MALLOC_LEN - sizeof(struct spare_boot_head_t);
#ifdef CONFIG_NONCACHE_MEMORY_SIZE
malloc_start &= (~(0x00100000 -1));
malloc_noncache_start = malloc_start - CONFIG_NONCACHE_MEMORY_SIZE;
gd->malloc_noncache_start = malloc_noncache_start;
#endif
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs();
#endif
#ifdef CONFIG_POST
post_output_backlog();
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#ifdef CONFIG_SMALL_MEMSIZE
save_config();
#endif
#ifdef CONFIG_NONCACHE_MEMORY
mem_noncache_malloc_init(malloc_noncache_start, CONFIG_NONCACHE_MEMORY_SIZE);
#endif
#if defined(CONFIG_ARCH_HOMELET)
check_physical_key_early();
#endif
workmode = uboot_spare_head.boot_data.work_mode;
debug("work mode %d\n", workmode);
axp_reinit();
//uboot_spare_head.boot_data.work_mode = WORK_MODE_CARD_PRODUCT;
#if defined(CONFIG_CPUS_STANDBY) //Ŀǰֻ��homelet��ʹ��
do_box_standby();
#endif
#ifdef CONFIG_ARCH_HOMELET
gpio_control();
#endif
#if 0
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
flash_size = flash_init();
if (flash_size > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv("flashchecksum");
if (s && (*s == 'y')) {
printf(" CRC: %08X", crc32(0,
(const unsigned char *) CONFIG_SYS_FLASH_BASE,
flash_size));
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
#endif
#endif
/* set up exceptions */
interrupt_init();
/* enable exceptions */
enable_interrupts();
sunxi_dma_init();
#ifdef CONFIG_USE_CIR //����ӿڣ�Ŀǰֻ���ں��� A20
if (uboot_spare_head.boot_data.work_mode == WORK_MODE_BOOT)
{
ir_setup();
}
#endif
#ifdef DEBUG
puts("ready to config storage\n");
#endif
#ifdef CONFIG_ARCH_HOMELET //for homlet to use one-key-recovery
ret = sunxi_flash_handle_init();
if(!ret)
{
sunxi_partition_init();
}
#endif
#ifndef CONFIG_ARCH_SUN8IW8P1
if((workmode == WORK_MODE_BOOT) || (workmode == WORK_MODE_CARD_PRODUCT) || (workmode == WORK_MODE_SPRITE_RECOVERY))
{
#else
if((workmode == WORK_MODE_CARD_PRODUCT) || (workmode == WORK_MODE_SPRITE_RECOVERY))
{
#endif
#if (defined(CONFIG_SUNXI_DISPLAY) || defined(CONFIG_SUN7I_DISPLAY))
drv_disp_init();
#endif
#ifdef CONFIG_SUNXI_HDCP_IN_SECURESTORAGE
int tmp = 0;
tmp = script_parser_fetch("hdmi_para", "hdmi_hdcp_enable", &hdcpkey_enable, 1);
if((tmp) || (hdcpkey_enable != 1))
{
board_display_device_open();
board_display_layer_request();
}
#else
board_display_device_open();
board_display_layer_request();
#endif
}
#ifndef CONFIG_ARCH_HOMELET //for pad used
ret = sunxi_flash_handle_init();
if(!ret)
{
sunxi_partition_init();
}
#endif
#ifdef CONFIG_SUNXI_HDCP_IN_SECURESTORAGE
//here: write key to hardware
if(hdcpkey_enable==1)
{
char buffer[4096];
int data_len;
int ret0;
memset(buffer, 0, 4096);
ret0 = sunxi_secure_storage_init();
if(ret0)
{
printf("sunxi init secure storage failed\n");
}
else
{
ret0 = sunxi_secure_object_read("hdcpkey", buffer, 4096, &data_len);
if(ret0)
{
printf("probe hdcp key failed\n");
}
else
{
ret0 = smc_aes_bssk_decrypt_to_keysram(buffer, data_len);
if(ret0)
{
printf("push hdcp key failed\n");
}
else
{
board_display_device_open();
board_display_layer_request();
}
}
}
}
#endif
#ifdef CONFIG_BOOT_A15
if(sunxi_sprite_download_boot0_simple())
{
printf("rewrite boot0 to save boot cpu failed\n");
}
#endif
#ifndef CONFIG_SUNXI_SPINOR_PLATFORM
sunxi_keydata_burn_by_usb();
#endif
//#else
//#if defined(CONFIG_CMD_NAND)
// if(!storage_type){
// puts("NAND: ");
// nand_init(); /* go init the NAND */
// }
//#endif/*CONFIG_CMD_NAND*/
//
//#if defined(CONFIG_GENERIC_MMC)
// if(storage_type){
// puts("MMC: ");
// mmc_initialize(bd);
// }
//#endif/*CONFIG_GENERIC_MMC*/
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
/* initialize environment */
env_relocate();
/* setenv storage_type */
sprintf(storage_type_buf, "%d", uboot_spare_head.boot_data.storage_type);
if (setenv("storage_type", storage_type_buf))
printf("set storage_type=%s fail\n", storage_type_buf);
if (uboot_spare_head.boot_data.storage_type == 1)
sprintf(boot_mmc_buf, "%s", "0");
else
sprintf(boot_mmc_buf, "%s", "2");
setenv("boot_mmc", boot_mmc_buf);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
arm_pci_init();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr("ipaddr");
stdio_init(); /* get the devices list going. */
jumptable_init();
#if defined(CONFIG_API)
/* Initialize API */
api_init();
#endif
console_init_r(); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r();
#endif
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
s = getenv("loadaddr");
if (s != NULL)
load_addr = simple_strtoul(s, NULL, 16);
#if defined(CONFIG_CMD_NET)
s = getenv("bootfile");
if (s != NULL)
copy_filename(BootFile, s, sizeof(BootFile));
#endif
#ifdef BOARD_LATE_INIT
board_late_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
* taking into account the protected RAM at top of memory
*/
{
ulong pram;
uchar memsz[32];
#ifdef CONFIG_PRAM
char *s;
s = getenv("pram");
if (s != NULL)
pram = simple_strtoul(s, NULL, 10);
else
pram = CONFIG_PRAM;
#else
pram = 0;
#endif
#ifdef CONFIG_LOGBUFFER
#ifndef CONFIG_ALT_LB_ADDR
/* Also take the logbuffer into account (pram is in kB) */
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif
//sprite_cartoon_test();
if(workmode == WORK_MODE_BOOT)
{
#if defined(CONFIG_SUNXI_SCRIPT_REINIT)
{
FATFS script_mount;
int ret;
uint read_bytes = 0;
FILE script_fs;
uchar *buf = NULL;
f_mount_ex(0, &script_mount, 0);
ret = f_open (&script_fs, "0:script.bin", FA_OPEN_EXISTING | FA_READ | FA_WRITE );
if(ret)
{
printf("cant open script.bin, maybe it is not exist\n");
}
else
{
buf = (uchar *)malloc(100 * 1024);
memset(buf, 0, 100 * 1024);
if(!f_read(&script_fs, buf, 100 * 1024, &read_bytes))
{
printf("f_read read bytes = %d\n", read_bytes);
}
f_close(&script_fs);
puts("try to unlink file ");
printf("%d\n", f_unlink("0:script.bin"));
}
f_mount(0, NULL, NULL);
if(read_bytes > 0)
{
char *tmp_target_buffer = (char *)(CONFIG_SYS_TEXT_BASE - 0x01000000);
sunxi_flash_exit(1);
memcpy(tmp_target_buffer + uboot_spare_head.boot_head.uboot_length, buf, read_bytes);
sunxi_sprite_download_uboot(tmp_target_buffer, uboot_spare_head.boot_data.storage_type, 1);
reset_cpu(0);
}
if(buf)
{
free(buf);
}
}
#endif
printf("WORK_MODE_BOOT\n");
#if (defined(CONFIG_SUNXI_DISPLAY) || defined(CONFIG_SUN7I_DISPLAY))
if(!ret)
{
#ifndef CONFIG_ARCH_HOMELET
printf("board_status_probe\n");
board_status_probe(0);
#endif
if(!gd->chargemode)
{
if(sunxi_advert_disp_probe())
{
printf("sunxi_bmp_logo_display\n");
sunxi_bmp_display("bootlogo.bmp");
}
else
{
if(sunxi_advert_display("Reserve0", "advert.bmp"))
{
printf("sunxi_bmp_logo_display\n");
sunxi_bmp_display("bootlogo.bmp");
}
}
}
else
{
printf("sunxi_bmp_charger_display\n");
sunxi_bmp_display("bat\\battery_charge.bmp");
}
}
#endif
#ifdef CONFIG_READ_LOGO_FOR_KERNEL
sunxi_read_bootlogo("boot_logo");
#endif
}
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;)
{
main_loop();
}
hang();
/* NOTREACHED - no way out of command loop except booting */
}
void hang(void)
{
puts("### ERROR ### Please RESET the board ###\n");
for (;;);
}
void board_init_f(ulong bootflag)
{
cmd_tbl_t *cmdtp;
bd_t *bd;
unsigned char *s;
init_fnc_t **init_fnc_ptr;
int j;
int i;
char *e;
#ifndef CONFIG_SYS_NO_FLASH
ulong flash_size;
#endif
gd = (gd_t *) (CONFIG_SYS_GBL_DATA_OFFSET);
/* Clear initial global data */
memset((void *)gd, 0, sizeof(gd_t));
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_RAM_BASE;
bd->bi_memsize = CONFIG_SYS_RAM_SIZE;
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
#endif
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
gd->reloc_off = CONFIG_SYS_RELOC_MONITOR_BASE - CONFIG_SYS_MONITOR_BASE;
for (init_fnc_ptr = init_sequence, j = 0; *init_fnc_ptr;
++init_fnc_ptr, j++) {
#ifdef DEBUG_INIT_SEQUENCE
if (j > 9)
str_init_seq[9] = '0' + (j / 10);
str_init_seq[10] = '0' + (j - (j / 10) * 10);
serial_puts(str_init_seq);
#endif
if ((*init_fnc_ptr + gd->reloc_off) () != 0) {
hang();
}
}
#ifdef DEBUG_INIT_SEQUENCE
serial_puts(str_init_seq_done);
#endif
/*
* Now that we have DRAM mapped and working, we can
* relocate the code and continue running from DRAM.
*
* Reserve memory at end of RAM for (top down in that order):
* - kernel log buffer
* - protected RAM
* - LCD framebuffer
* - monitor code
* - board info struct
*/
#ifdef DEBUG_MEM_LAYOUT
printf("CONFIG_SYS_MONITOR_BASE: 0x%lx\n", CONFIG_SYS_MONITOR_BASE);
printf("CONFIG_ENV_ADDR: 0x%lx\n", CONFIG_ENV_ADDR);
printf("CONFIG_SYS_RELOC_MONITOR_BASE: 0x%lx (%d)\n", CONFIG_SYS_RELOC_MONITOR_BASE,
CONFIG_SYS_MONITOR_LEN);
printf("CONFIG_SYS_MALLOC_BASE: 0x%lx (%d)\n", CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_LEN);
printf("CONFIG_SYS_INIT_SP_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_INIT_SP_OFFSET,
CONFIG_SYS_STACK_SIZE);
printf("CONFIG_SYS_PROM_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_PROM_OFFSET,
CONFIG_SYS_PROM_SIZE);
printf("CONFIG_SYS_GBL_DATA_OFFSET: 0x%lx (%d)\n", CONFIG_SYS_GBL_DATA_OFFSET,
CONFIG_SYS_GBL_DATA_SIZE);
#endif
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(0));
#endif
/*
* We have to relocate the command table manually
*/
for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
ulong addr;
addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
#if DEBUG_COMMANDS
printf("Command \"%s\": 0x%08lx => 0x%08lx\n",
cmdtp->name, (ulong) (cmdtp->cmd), addr);
#endif
cmdtp->cmd =
(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
addr = (ulong) (cmdtp->name) + gd->reloc_off;
cmdtp->name = (char *)addr;
if (cmdtp->usage) {
addr = (ulong) (cmdtp->usage) + gd->reloc_off;
cmdtp->usage = (char *)addr;
}
#ifdef CONFIG_SYS_LONGHELP
if (cmdtp->help) {
addr = (ulong) (cmdtp->help) + gd->reloc_off;
cmdtp->help = (char *)addr;
}
#endif
}
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
puts("AMBA:\n");
do_ambapp_print(NULL, 0, 0, NULL);
#endif
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r();
/* start timer */
timer_interrupt_init();
/*
* Enable Interrupts before any calls to udelay,
* the flash driver may use udelay resulting in
* a hang if not timer0 IRQ is enabled.
*/
interrupt_init();
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE);
malloc_bin_reloc();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("FLASH: ");
if ((flash_size = flash_init()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size(flash_size, "");
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
*/
s = getenv("flashchecksum");
if (s && (*s == 'y')) {
printf(" CRC: %08lX",
crc32(0, (const unsigned char *)CONFIG_SYS_FLASH_BASE,
flash_size)
);
}
putc('\n');
# else /* !CONFIG_SYS_FLASH_CHECKSUM */
print_size(flash_size, "\n");
# endif /* CONFIG_SYS_FLASH_CHECKSUM */
} else {
puts(failed);
hang();
}
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
#else
bd->bi_flashoffset = 0;
#endif
#else /* CONFIG_SYS_NO_FLASH */
bd->bi_flashsize = 0;
bd->bi_flashstart = 0;
bd->bi_flashoffset = 0;
#endif /* !CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_SPI
# if !defined(CONFIG_ENV_IS_IN_EEPROM)
spi_init_f();
# endif
spi_init_r();
#endif
/* relocate environment function pointers etc. */
env_relocate();
#if defined(CONFIG_BOARD_LATE_INIT)
board_late_init();
#endif
#ifdef CONFIG_ID_EEPROM
mac_read_from_eeprom();
#endif
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr("ipaddr");
#if defined(CONFIG_PCI)
/*
* Do pci configuration
*/
pci_init();
#endif
/* Initialize stdio devices */
stdio_init();
/* Initialize the jump table for applications */
jumptable_init();
/* Initialize the console (after the relocation and devices init) */
console_init_r();
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
serial_buffered_init();
#endif
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
udelay(20);
set_timer(0);
/* Initialize from environment */
if ((s = getenv("loadaddr")) != NULL) {
load_addr = simple_strtoul(s, NULL, 16);
}
#if defined(CONFIG_CMD_NET)
if ((s = getenv("bootfile")) != NULL) {
copy_filename(BootFile, s, sizeof(BootFile));
}
#endif /* CONFIG_CMD_NET */
WATCHDOG_RESET();
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET();
puts("DOC: ");
doc_init();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET();
puts("Net: ");
#endif
eth_initialize(bd);
#endif
#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
WATCHDOG_RESET();
debug("Reset Ethernet PHY\n");
reset_phy();
#endif
#ifdef CONFIG_POST
post_run(NULL, POST_RAM | post_bootmode_get(0));
#endif
#if defined(CONFIG_CMD_IDE)
WATCHDOG_RESET();
puts("IDE: ");
ide_init();
#endif /* CONFIG_CMD_IDE */
#ifdef CONFIG_LAST_STAGE_INIT
WATCHDOG_RESET();
/*
* Some parts can be only initialized if all others (like
* Interrupts) are up and running (i.e. the PC-style ISA
* keyboard).
*/
last_stage_init();
#endif
#ifdef CONFIG_PS2KBD
puts("PS/2: ");
kbd_init();
#endif
prom_init();
/* main_loop */
for (;;) {
WATCHDOG_RESET();
main_loop();
}
}
void start_arcboot(void)
{
DECLARE_GLOBAL_DATA_PTR;
static gd_t gd_data;
static bd_t bd_data;
init_fnc_t **init_fnc_ptr;
extern void *__text_end;
unsigned stage = sizeof(init_sequence)/sizeof(init_sequence[0]);
show_boot_progress(stage--);
/* Init Global Data */
gd = global_data = &gd_data;
gd->bd = &bd_data;
gd->cpu_clk=get_cpu_clk();
gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET;
gd->bd->bi_memstart=PHYS_MEMORY_START;
gd->bd->bi_memsize=PHYS_MEMORY_SIZE;
gd->bd->bi_flashstart=CONFIG_SYS_FLASH_BASE;
gd->bd->bi_flashoffset=0;
/* frame buffer will sit after end of program */
gd->fb_base = TEXT_BASE;
for (init_fnc_ptr = init_sequence;*init_fnc_ptr;++init_fnc_ptr) {
show_boot_progress(stage--);
if ((*init_fnc_ptr)() != 0) {
printf("stage:%d",stage);
hang();
}
}
/* Setup malloc area */
mem_malloc_init((ulong)&_start - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
// __builtin_arc_sleep(0);
#ifdef CONFIG_CMD_NAND
puts ("NAND: ");
nand_init();
#endif
env_relocate();
stdio_init (); /* get the devices list going. */
jumptable_init();
console_init_r();
#ifdef CONFIG_MMC
mmc_initialize(&bd_data);
#endif
#ifdef CONFIG_CMD_NET
puts ("Net: ");
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
// eth_io_init();
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug ("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init ();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r ();
#endif
#if defined(CONFIG_CMD_KGDB)
puts("KGDB: ");
kgdb_init();
#endif
/* enable exceptions */
enable_interrupts ();
icache_enable();
dcache_enable();
printf("Dcache status %d\n",dcache_status());
printf("Icache status %d\n",icache_status());
#ifdef CONFIG_A3_DISPLAY
osd_display();
#endif
#ifdef CONFIG_A3_I2C
disable_i2c_pinmux();//disable hard i2c pinmux
#endif
// kgdb_test();
// init_osd_dev() ;
for(;;){
main_loop();
}
}
