/* SCL Divisor = 8 * (CLKDIVL + CLKDIVH)
* SCL = i2c_rate/ SCLK Divisor
*/
static void rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate)
{
unsigned long i2c_rate = clk_get_rate(i2c->clk);
unsigned int div, divl, divh;
if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate))
return;
i2c->i2c_rate = i2c_rate;
i2c->scl_rate = scl_rate;
div = rk30_ceil(i2c_rate, scl_rate * 8);
divh = divl = rk30_ceil(div, 2);
i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV);
i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV));
return;
}
void __sramfunc sram_i2c_init()
{
unsigned int div, divl, divh;
//enable cru_clkgate8 clock
data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8)));
cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1),
CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1));
data[2] = readl_relaxed(RK30_GRF_BASE + GRF_GPIO_IOMUX);
writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK30_GRF_BASE + GRF_GPIO_IOMUX);
div = rk30_ceil(24*1000*1000, I2C_SPEED*1000 * 8);
divh = divl = rk30_ceil(div, 2);
writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV);
data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV);
}
