static void rtl8169_update_stat(re_t *rep)
{
port_t port;
int i;
port = rep->re_base_port;
/* Fetch Missed Packets */
rep->re_stat.ets_missedP += rl_inw(port, RL_MPC);
rl_outw(port, RL_MPC, 0x00);
/* Dump Tally Counter Command */
rl_outl(port, RL_DTCCR_HI, 0); /* 64 bits */
rl_outl(port, RL_DTCCR_LO, rep->dtcc_buf | RL_DTCCR_CMD);
for (i = 0; i < 1000; i++) {
if (!(rl_inl(port, RL_DTCCR_LO) & RL_DTCCR_CMD))
break;
micro_delay(10);
}
/* Update counters */
rep->re_stat.ets_frameAll = rep->v_dtcc_buf->FAE;
rep->re_stat.ets_transDef = rep->v_dtcc_buf->TxUndrn;
rep->re_stat.ets_transAb = rep->v_dtcc_buf->TxAbt;
rep->re_stat.ets_collision =
rep->v_dtcc_buf->Tx1Col + rep->v_dtcc_buf->TxMCol;
}
static void rtl8169_update_stat(re_t *rep)
{
static u64_t last_miss = 0, last_coll = 0;
u64_t miss, coll;
port_t port;
int i;
port = rep->re_base_port;
/* Dump Tally Counter Command */
rl_outl(port, RL_DTCCR_HI, 0); /* 64 bits */
rl_outl(port, RL_DTCCR_LO, rep->dtcc_buf | RL_DTCCR_CMD);
for (i = 0; i < 1000; i++) {
if (!(rl_inl(port, RL_DTCCR_LO) & RL_DTCCR_CMD))
break;
micro_delay(10);
}
/* Update counters */
miss = rep->v_dtcc_buf->MissPkt;
netdriver_stat_ierror(miss - last_miss);
last_miss = miss;
coll = rep->v_dtcc_buf->Tx1Col + rep->v_dtcc_buf->TxMCol;
netdriver_stat_coll(coll - last_coll);
last_coll = coll;
}
static int mdio_read(u16_t port, int regaddr)
{
int i, value = -1;
rl_outl(port, RL_PHYAR, (regaddr & 0x1F) << 16);
for (i = 20; i > 0; i--) {
/*
* Check if the RTL8169 has completed retrieving data from
* the specified MII register
*/
if (rl_inl(port, RL_PHYAR) & 0x80000000) {
value = (int)(rl_inl(port, RL_PHYAR) & 0xFFFF);
break;
} else
micro_delay(50);
}
return value;
}
static void mdio_write(u16_t port, int regaddr, int value)
{
int i;
rl_outl(port, RL_PHYAR, 0x80000000 | (regaddr & 0x1F) << 16 | (value & 0xFFFF));
for (i = 20; i > 0; i--) {
/*
* Check if the RTL8169 has completed writing to the specified
* MII register
*/
if (!(rl_inl(port, RL_PHYAR) & 0x80000000))
break;
else
micro_delay(50);
}
}
