static int rotator_dst_set_addr(struct device *dev, dma_addr_t *base, u32 id, enum drm_exynos_ipp_buf_ctrl ctrl) { struct rot_context *rot = dev_get_drvdata(dev); dma_addr_t addr[EXYNOS_DRM_PLANER_MAX]; struct drm_exynos_ipp_property *property = &rot->property; struct drm_exynos_ipp_config *config = &property->config[EXYNOS_DRM_OPS_DST]; int i; /* Check ctrl */ switch (ctrl) { case IPP_BUF_CTRL_MAP: case IPP_BUF_CTRL_UNMAP: /* Set address configuration */ for (i = 0; i < EXYNOS_DRM_PLANER_MAX; i++) addr[i] = base[i]; /* Re-set address of CB(CR) for NV12 format case */ if ((ctrl == IPP_BUF_CTRL_MAP) && (config->fmt == DRM_FORMAT_NV12)) addr[EXYNOS_DRM_PLANER_CB] = addr[EXYNOS_DRM_PLANER_Y] + config->pos.w * config->pos.h; for (i = 0; i < EXYNOS_DRM_PLANER_MAX; i++) rotator_reg_set_dst_buf_addr(rot, addr[i], i); break; default: /* Nothing to do */ break; } return 0; }
static int rotator_dst_set_addr(struct device *dev, struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, enum drm_exynos_ipp_buf buf) { struct rot_context *rot = dev_get_drvdata(dev); dma_addr_t addr[EXYNOS_DRM_PLANAR_MAX]; u32 fmt, hsize, vsize; int i; /* Set current buf_id */ rot->cur_buf_id[EXYNOS_DRM_OPS_DST] = buf_id; switch (buf) { case IPP_BUF_ENQUEUE: /* Set address configuration */ for_each_ipp_planar(i) addr[i] = buf_info->base[i]; /* Get format */ fmt = rotator_reg_get_format(rot); /* Re-set cb planar for NV12 format */ if ((fmt == ROT_CONTROL_FMT_YCBCR420_2P) && (addr[EXYNOS_DRM_PLANAR_CB] == 0x00)) { /* Get buf size */ rotator_reg_get_dst_buf_size(rot, &hsize, &vsize); /* Set cb planar */ addr[EXYNOS_DRM_PLANAR_CB] = addr[EXYNOS_DRM_PLANAR_Y] + hsize * vsize; } for_each_ipp_planar(i) rotator_reg_set_dst_buf_addr(rot, addr[i], i); break; case IPP_BUF_DEQUEUE: for_each_ipp_planar(i) rotator_reg_set_dst_buf_addr(rot, buf_info->base[i], i); break; default: /* Nothing to do */ break; } return 0; }