int gfxnvidia_init(void) { uint32_t reg32; if (rget_io_perms()) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) return 1; /* Allow access to flash interface (will disable screen). */ reg32 = pci_read_long(pcidev_dev, 0x50); reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); /* Write/erase doesn't work. */ programmer_may_write = 0; register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; }
int gfxnvidia_init(void) { uint32_t reg32; get_io_perms(); io_base_addr = pcidev_init(PCI_VENDOR_ID_NVIDIA, PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); /* Allow access to flash interface (will disable screen). */ reg32 = pci_read_long(pcidev_dev, 0x50); reg32 &= ~(1 << 0); rpci_write_long(pcidev_dev, 0x50, reg32); nvidia_bar = physmap("NVIDIA", io_base_addr, 16 * 1024 * 1024); buses_supported = CHIP_BUSTYPE_PARALLEL; /* Write/erase doesn't work. */ programmer_may_write = 0; return 0; }
int atahpt_init(void) { struct pci_dev *dev = NULL; uint32_t reg32; if (rget_io_perms()) return 1; dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4); if (!dev) return 1; io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); if (!io_base_addr) return 1; /* Enable flash access. */ reg32 = pci_read_long(dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); rpci_write_long(dev, REG_FLASH_ACCESS, reg32); register_par_master(&par_master_atahpt, BUS_PARALLEL); return 0; }