int rtapi_app_main(void)
{
int n;
board_data_t *pboard;
struct pci_dev *pDev;
// Connect to the HAL.
driver.comp_id = hal_init("opto_ac5");
if (driver.comp_id < 0) {
rtapi_print_msg(RTAPI_MSG_ERR, " ERROR OPTO_AC5--- hal_init() failed\n");
return(-1);
}
for ( n = 0 ; n < MAX_BOARDS ; n++ ) {
driver.boards[n] = NULL;
}
pDev = NULL;
for ( n = 0 ; n < MAX_BOARDS ; n++ )
{
// Find a M5I20 card.
pDev = pci_get_device(opto22_VENDOR_ID, opto22_pci_AC5_DEVICE_ID, pDev);
if ( pDev == NULL ) {
/* no more boards */break;
}
/* Allocate HAL memory for the board */
pboard = (board_data_t *)(hal_malloc(sizeof(board_data_t)));
if ( pboard == NULL ) {
rtapi_print_msg(RTAPI_MSG_ERR, "ERROR OPTO_AC5--- hal_malloc() failed\n");
rtapi_app_exit();
return -1;
}
// save pointer
driver.boards[n] = pboard;
/* gather info about the board and save it */
pboard->pci_dev = pDev;
pboard->slot = PCI_SLOT(pDev->devfn);
pboard->num = n;
rtapi_print("INFO OPTO_AC5--- Board %d detected in PCI Slot: %2x\n", pboard->num, pboard->slot);
/* region 0 is the 32 bit memory mapped I/O region */
pboard->len = pci_resource_len(pDev, 0);
pboard->base = ioremap_nocache(pci_resource_start(pDev, 0), pboard->len);
if ( pboard->base == NULL ) {
rtapi_print_msg(RTAPI_MSG_ERR,
"ERROR OPTO_AC5--- could not find board %d PCI base address\n", pboard->num );
rtapi_app_exit();
return -1;
} else {
rtapi_print(
"INFO OPTO_AC5--- board %d mapped to %08lx, Len = %ld\n",
pboard->num, (long)pboard->base,(long)pboard->len);
}
// Initialize device.
if(Device_Init(pboard)) {
hal_exit(driver.comp_id);
return(-1);
}
// Export pins, parameters, and functions.
if(Device_ExportPinsParametersFunctions(pboard, driver.comp_id, n)) {
hal_exit(driver.comp_id);
return(-1);
}
}
if(n == 0) {
/* No cards detected */
rtapi_print ("ERROR OPTO_AC5--- No opto PCI-AC5 card(s) detected\n");
rtapi_app_exit();
return(-1);
}
hal_ready(driver.comp_id);
return(0);
}
int rtapi_app_main(void)
{
int retval, i;
int in_cnt = 0, out_cnt = 0;
char buf[128];
char *pc = axes_conf;
/* Parsing axes configuration */
while(*pc != 0)
{
int idx = -1;
switch(*pc)
{
case 'X':
case 'x':
idx = 0;
break;
case 'Y':
case 'y':
idx = 1;
break;
case 'Z':
case 'z':
idx = 2;
break;
case 'A':
case 'a':
idx = 3;
break;
case 'B':
case 'b':
idx = 4;
break;
case 'C':
case 'c':
idx = 5;
break;
default: break;
}
if(idx >= 0)
axis_map[num_axis++] = idx;
pc++;
}
fprintf(stderr, "num_axis=%d, fifo_size=%d\n", num_axis, fifo_deep);
/* test for number of channels */
if ((num_axis <= 0) || (num_axis > MAX_AXIS)) {
rtapi_print_msg(RTAPI_MSG_ERR,
"miniemcdrv: ERROR: invalid num_chan: %d\n", num_axis);
return -EINVAL;
}
/* have good config info, connect to the HAL */
comp_id = hal_init("miniemcdrv");
if (comp_id < 0)
{
rtapi_print_msg(RTAPI_MSG_ERR, "miniemcdrv: ERROR: hal_init() failed\n");
rtapi_app_exit();
return -EINVAL;
}
pgpio = hal_malloc(sizeof(gpio_t));
memset(pgpio, 0, sizeof(gpio_t));
pgpio->fd = open("/dev/miniemc", O_RDWR | O_SYNC);
if(pgpio->fd < 0)
{
rtapi_print_msg(RTAPI_MSG_ERR,
"miniemcdrv: ERROR: unble to create access to stepgen module\n");
rtapi_app_exit();
return -EIO;
}
pgpio->pfiq = mmap(0, sizeof(struct fiq_ipc_shared), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, pgpio->fd, 0);
if(pgpio->pfiq == MAP_FAILED)
{
rtapi_print_msg(RTAPI_MSG_ERR,
"miniemcdrv: ERROR: unable to mmap stepgen ringbuffer\n");
rtapi_app_exit();
return -EIO;
}
/* Setup ringbuff size */
fiq_static.rb_size = fifo_deep;
memset(&cmd_pos_prev, 0, sizeof(cmd_pos_prev));
memset(&cmd_pos_accum, 0, sizeof(cmd_pos_accum));
//Configure PWM pins and create HAL inputs
for( i = 0; i < MAX_PWM; i++)
{
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.pwm-in", i);
retval = hal_pin_float_new(buf, HAL_IN, &(pgpio->pwm_duty[i]), comp_id);
if (retval != 0)
{
rtapi_app_exit();
return retval;
}
if( pwm_pin_num[i] >= 0 )
{
emcConfigureDefault( pwm_pin_num[i] );
emcReservePin( pwm_pin_num[i] );
fiq_static.pwm_pin_addr[i] = GPIOS[pwm_pin_num[i]].port_index;
fiq_static.pwm_pin_mask[i] = 1L << GPIOS[pwm_pin_num[i]].offset;
pgpio->pfiq->pwm_duty_cycle[i] = 0;
} else
{
fiq_static.pwm_pin_mask[i] = 0;
fiq_static.pwm_pin_addr[i] = 0;
}
}
// Create axis step and dir pins
for(i = 0; i < num_axis; i++)
{
if(step_pins[i] >=0 && dir_pins[i] >= 0)
{
if( emcGetPinMode( step_pins[i]) == egpIn || emcGetPinMode( dir_pins[i]) == egpIn )
{
rtapi_print_msg(RTAPI_MSG_ERR, "WARN: can't create axis[%d] stepgen, invalid pin\n", i);
continue;
}
fiq_static.axis[i].configured = 0;
fiq_static.axis[i].step_pin_addr = GPIOS[step_pins[i]].port_index;
fiq_static.axis[i].step_pin_mask = 1L << GPIOS[step_pins[i]].offset;
emcConfigureDefault( step_pins[i] );
emcReservePin( step_pins[i] );
fiq_static.axis[i].dir_pin_addr = GPIOS[dir_pins[i]].port_index;
fiq_static.axis[i].dir_pin_mask = 1L << GPIOS[dir_pins[i]].offset;
emcConfigureDefault( dir_pins[i] );
emcReservePin( dir_pins[i] );
fiq_static.axis[i].dir_pin_pol = dir_polarity[i];
fiq_static.axis[i].configured = 1;
} else
{
rtapi_print_msg(RTAPI_MSG_ERR,
"miniemcdrv: WARNING: axis[%d] step and/or dir pin(s) not properly configured, skipping\n", i);
}
fiq_static.scan_pin_num = -1;
}
ioctl(pgpio->fd, AXIS_SET_IOCTL, &fiq_static );
/*
* Create IO pins
*/
for( i=0; i < ARR_SZ(GPIOS); i++ )
{
if( emcGetPinMode( i ) == egpRsv )
continue;
if( emcGetPinMode( i ) == egpIn )
{
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.pin-in", in_cnt);
hal_pin_bit_new(buf, HAL_OUT, &(pgpio->io_pin[i]), comp_id);
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.pin-in-inv", in_cnt);
hal_pin_bit_new(buf, HAL_IN, &(pgpio->io_invert[i]), comp_id);
in_cnt++;
} else
{
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.pin-out", out_cnt);
hal_pin_bit_new(buf, HAL_IN, &(pgpio->io_pin[i]), comp_id);
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.pin-out-inv", out_cnt);
hal_pin_bit_new(buf, HAL_IN, &(pgpio->io_invert[i]), comp_id);
out_cnt++;
}
emcConfigureDefault( i );
}
// Trajectory wait output
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.traj-wait-out");
hal_pin_bit_new(buf, HAL_OUT, &(pgpio->traj_wait), comp_id);
*(pgpio->traj_wait) = 1;
// Scaner sync
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.scan-sync-in");
hal_pin_bit_new(buf, HAL_IN, &(pgpio->scan_sync), comp_id);
for(i=0; i < num_axis; i++)
{
// Check if pin already added
char contin = 0;
int j;
for(j=0; j < i; j++)
if(axis_map[j] == axis_map[i])
{
contin = 1;
break;
}
if(contin) continue;
// commanded position pin
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.cmd-pos", axis_map[i]);
retval = hal_pin_float_new(buf, HAL_IN, &(pgpio->cmd_pos[axis_map[i]]), comp_id);
if (retval != 0)
{
rtapi_app_exit();
return retval;
}
//feedback position pin
rtapi_snprintf(buf, HAL_NAME_LEN, "miniemcdrv.%d.fb-pos", axis_map[i]);
retval = hal_pin_float_new(buf, HAL_OUT, &(pgpio->fb_pos[axis_map[i]]), comp_id);
if (retval != 0)
{
rtapi_app_exit();
return retval;
}
}
/* export functions */
retval = hal_export_funct("update-miniemcdrv", update,
pgpio, 0, 0, comp_id);
if (retval != 0)
{
rtapi_print_msg(RTAPI_MSG_ERR,
"miniemcdrv: ERROR: count funct export failed\n");
rtapi_app_exit();
return -EIO;
}
ioctl(pgpio->fd, SCAN_PIN_SETUP_IOCTL, NULL);
//emcConfigurePin(11, egpOut );
//emcSetPin(11, 1 );
hal_ready(comp_id);
return 0;
}
