示例#1
0
static void REGPARAM2 rtarea_wput (uaecptr addr, uae_u32 value)
{
	addr &= 0xffff;
	value &= 0xffff;

	if (addr & 1)
		return;

	if (!rtarea_write(addr))
		return;

	uaecptr addr2 = addr - RTAREA_TRAP_STATUS;

	if (rtarea_trap_status(addr)) {
		int trap_offset = addr2 & (RTAREA_TRAP_STATUS_SIZE - 1);
		int trap_slot = addr2 / RTAREA_TRAP_STATUS_SIZE;
		if (trap_offset == 2) {
			value = 0;
			if ((rtarea_bank.baseaddr[addr + 1] & 0x80) == 0) {
				write_log(_T("TRAP SLOT %d unlock without allocation!\n"), trap_slot);
			}
			rtarea_bank.baseaddr[addr + 0] = value >> 8;
			rtarea_bank.baseaddr[addr + 1] = (uae_u8)value;
			return;
		}
	}
示例#2
0
static void REGPARAM2 rtarea_bput (uaecptr addr, uae_u32 value)
{
	addr &= 0xffff;
	if (!rtarea_write(addr))
		return;
	rtarea_bank.baseaddr[addr] = value;
	if (addr == RTAREA_INTREQ + 3) {
		mousehack_wakeup();
	}
	if (!rtarea_trap_status(addr))
		return;
	addr -= RTAREA_TRAP_STATUS;
	int trap_offset = addr & (RTAREA_TRAP_STATUS_SIZE - 1);
	int trap_slot = addr / RTAREA_TRAP_STATUS_SIZE;
#if NEW_TRAP_DEBUG
	write_log(_T("PUT TRAP SLOT %d OFFSET %d: V=%02x\n"), trap_slot, trap_offset, (uae_u8)value);
#endif
	if (trap_offset == RTAREA_TRAP_STATUS_SECOND) {
		write_log(_T("TRAP SLOT %d PRI=%02x\n"), trap_slot, (uae_u8)value);
	}
	if (trap_offset == RTAREA_TRAP_STATUS_SECOND + 3) {
		uae_u8 v = (uae_u8)value;
		if (v != 0xff && v != 0xfd && v != 0x01 && v != 0x02 && v != 0x03 && v != 0x04)
			write_log(_T("TRAP SLOT %d STATUS = %02x\n"), trap_slot, v);
		if (v == 0xfd)
			atomic_dec(&hwtrap_waiting);
		if (v == 0x01)
			atomic_dec(&hwtrap_waiting);
		// 1 = interrupt ack
		// 2 = interrupt -> task ack
		// 3 = hwtrap_entry ack
		if (v == 0x01 || v == 0x02 || v == 0x03) {
			// signal call_hardware_trap_back_back()
			uae_sem_post(&hardware_trap_event[trap_slot]);
		}
	}
}