/* rtc init check */
int rtc_init(u8 recover)
{
int ret;
rtc_info("recovery: %d\n", recover);
/* write powerkeys to enable rtc functions */
if (!rtc_powerkey_init()) {
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
goto err;
}
/* write interface unlock need to be set after powerkey match */
if (!rtc_writeif_unlock()) {
ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
goto err;
}
/* using dcxo 32K clock */
if (!rtc_enable_dcxo()) {
ret = -RTC_STATUS_OSC_SETTING_FAIL;
goto err;
}
if (recover)
mdelay(20);
if (!rtc_gpio_init()) {
ret = -RTC_STATUS_GPIO_INIT_FAIL;
goto err;
}
if (!rtc_hw_init()) {
ret = -RTC_STATUS_HW_INIT_FAIL;
goto err;
}
if (!rtc_reg_init()) {
ret = -RTC_STATUS_REG_INIT_FAIL;
goto err;
}
if (!rtc_lpd_init()) {
ret = -RTC_STATUS_LPD_INIT_FAIL;
goto err;
}
/* After lpd init, powerkeys need to be written again to enable
* low power detect function.
*/
if (!rtc_powerkey_init()) {
ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
goto err;
}
return RTC_STATUS_OK;
err:
rtc_info("init fail: ret=%d\n", ret);
return ret;
}
/* initialize rtc setting of using dcxo clock */
static int rtc_enable_dcxo(void)
{
u16 bbpu, con, osc32con, sec;
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
mdelay(1);
if (!rtc_writeif_unlock()) { /* Unlock for reload */
rtc_info("rtc_writeif_unlock() fail\n");
return 0;
}
rtc_read(RTC_OSC32CON, &osc32con);
osc32con &= ~RTC_EMBCK_SRC_SEL;
osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB;
if (!rtc_xosc_write(osc32con)) {
rtc_info("rtc_xosc_write() fail\n");
return 0;
}
rtc_read(RTC_BBPU, &bbpu);
rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
rtc_write_trigger();
rtc_read(RTC_CON, &con);
rtc_read(RTC_OSC32CON, &osc32con);
rtc_read(RTC_AL_SEC, &sec);
rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);
return 1;
}
void poweroff(void)
{
u16 bbpu;
if (!rtc_writeif_unlock())
rtc_info("rtc_writeif_unlock() fail\n");
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_RELOAD | RTC_BBPU_PWREN;
rtc_write(RTC_BBPU, bbpu);
pmic_set_power_hold(false);
halt();
}
void mt6575_sleep(u32 timeout, kal_bool en_deep_idle)
{
unsigned int topmisc, pdn0;
printf("enter mt6575_sleep, timeout = %d\n", timeout);
#if MT6575_SC_DEBUG
slp_dump_pm_regs();
#endif
pdn0 = DRV_Reg32(PERI_GLOBALCON_PDN0);
if (get_chip_eco_ver() == CHIP_E1) {
/* power on UART0/1/2/3 to workaround handshake mode issue */
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0 & ~(0xf << 24));
}
/* keep CA9 clock when entering WFI mode in sleep */
topmisc = DRV_Reg32(TOP_MISC);
DRV_WriteReg32(TOP_MISC, topmisc & ~(1U << 0));
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) & 0x7FFF);
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) | 0x1);
}
}
rtc_writeif_lock();
sc_go_to_sleep(timeout, en_deep_idle);
rtc_writeif_unlock();
if (get_chip_eco_ver() != CHIP_E1) {
if (en_deep_idle) {
DRV_WriteReg32(MDPLL_CON0, DRV_Reg32(MDPLL_CON0) & 0xFFFE);
udelay(20);
DRV_WriteReg32(TOPCKGEN_CON3, DRV_Reg32(TOPCKGEN_CON3) | 0x8000);
}
}
/* restore TOP_MISC (and PERI_GLOBALCON_PDN0) */
DRV_WriteReg32(TOP_MISC, topmisc);
if (get_chip_eco_ver() == CHIP_E1)
DRV_WriteReg32(PERI_GLOBALCON_PDN0, pdn0);
return 0;
}
void rtc_bbpu_power_down(void)
{
u16 bbpu, con;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
rtc_writeif_unlock();
/* disable 32K export if there are no RTC_GPIO users */
if (!(rtc_read(RTC_PDN1) & RTC_GPIO_USER_MASK)) {
con = rtc_read(RTC_CON) | RTC_CON_F32KOB;
rtc_write(RTC_CON, con);
rtc_write_trigger();
con = rtc_read(RTC_OSC32CON) & ~RTC_OSC32CON_GPIOCKEN;
rtc_xosc_write(con, false);
}
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN;
rtc_write(RTC_BBPU, bbpu);
rtc_write_trigger();
spin_unlock_irqrestore(&rtc_lock, flags);
}
