void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data)
{
if (arg == ASF_GET)
data[ASFHBPERIOD] = rtl8168_eri_read(ioaddr, HBPeriod, RW_TWO_BYTES, ERIAR_ASF);
else if (arg == ASF_SET) {
rtl8168_eri_write(ioaddr, HBPeriod, RW_TWO_BYTES, data[ASFHBPERIOD], ERIAR_ASF);
rtl8168_eri_write(ioaddr, 0x1EC, RW_ONE_BYTE, 0x07, ERIAR_ASF);
}
}
void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data)
{
if (arg == ASF_GET)
data[ASFRWHEXNUM] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF);
else /* arg == ASF_SET */
rtl8168_eri_write(ioaddr, offset, len, data[ASFRWHEXNUM], ERIAR_ASF);
}
void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data)
{
if (arg == ASF_GET)
data[ASFCOMMULEN] = rtl8168_eri_read(ioaddr, StringLength, RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
rtl8168_eri_write(ioaddr, StringLength, RW_ONE_BYTE, data[ASFCOMMULEN], ERIAR_ASF);
}
void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
{
unsigned int len, bit_mask;
bit_mask = DISABLE_MASK;
if (offset == FmCapMsk) {
/* System firmware capabilities */
len = RW_FOUR_BYTES;
if (data[ASFCAPMASK] == FUNCTION_ENABLE)
bit_mask = FMW_CAP_MASK;
} else if (offset == SpCMDMsk) {
/* Special commands */
len = RW_TWO_BYTES;
if (data[ASFCAPMASK] == FUNCTION_ENABLE)
bit_mask = SPC_CMD_MASK;
} else {
/* System capability (offset == SysCapMsk)*/
len = RW_ONE_BYTE;
if (data[ASFCAPMASK] == FUNCTION_ENABLE)
bit_mask = SYS_CAP_MASK;
}
if (arg == ASF_GET)
data[ASFCAPMASK] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
else /* arg == ASF_SET */
rtl8168_eri_write(ioaddr, offset, len, bit_mask, ERIAR_ASF);
}
void rtl8168_asf_key_access(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
{
void __iomem *ioaddr=tp->mmio_addr;
int i, j;
int key_off = 0;
if (arg == ASF_GET) {
for (i = 0; i < KEY_LEN; i++)
data[i] = rtl8168_eri_read(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF);
} else {
if (offset == KO)
key_off = 162;
else if (offset == KA)
key_off = 172;
else if (offset == KG)
key_off = 182;
else if (offset == KR)
key_off = 192;
/* arg == ASF_SET */
for (i = 0; i < KEY_LEN; i++)
rtl8168_eri_write(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF);
/* write the new key to EEPROM */
for (i = 0, j = 19; i < 10; i++, j = j - 2)
rtl_eeprom_write_sc(tp, key_off + i, (data[j - 1] << 8) | data[j]);
}
}
void rtl8168_asf_key_access(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
{
int i;
if (arg == ASF_GET)
for (i = 0; i < KEY_LEN; i++)
data[i] = rtl8168_eri_read(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
for (i = 0; i < KEY_LEN; i++)
rtl8168_eri_write(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF);
}
void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data)
{
int i;
if (arg == ASF_GET)
for (i = 0; i < RW_FOUR_BYTES; i++)
data[i] = rtl8168_eri_read(ioaddr, IANA + i, RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
for (i = 0; i < RW_FOUR_BYTES; i++)
rtl8168_eri_write(ioaddr, IANA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
}
void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data)
{
int i, j;
if (arg == ASF_GET)
for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
data[j] = rtl8168_eri_read(ioaddr, UUID + i, RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
rtl8168_eri_write(ioaddr, UUID + i, RW_ONE_BYTE, data[j], ERIAR_ASF);
}
void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data)
{
int i;
if (arg == ASF_GET)
for (i = 0; i < SYSID_LEN ; i++)
data[i] = rtl8168_eri_read(ioaddr, SysID + i, RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
for (i = 0; i < SYSID_LEN ; i++)
rtl8168_eri_write(ioaddr, SysID + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
}
void rtl8168_asf_ip_address(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
{
int i;
if (arg == ASF_GET) {
for (i = 0; i < 4; i++)
data[i] = rtl8168_eri_read(ioaddr, offset + i, RW_ONE_BYTE, ERIAR_ASF);
} else if (arg == ASF_SET) {
for (i = 0; i < 4; i++)
rtl8168_eri_write(ioaddr, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
}
}
void rtl8168_asf_console_mac(void __iomem *ioaddr, int arg, unsigned int *data)
{
int i;
if (arg == ASF_GET) {
for (i = 0; i < 6; i++)
data[i] = rtl8168_eri_read(ioaddr, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF);
} else if (arg == ASF_SET) {
for (i = 0; i < 6; i++)
rtl8168_eri_write(ioaddr, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
}
}
void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string)
{
int i;
if (arg == ASF_GET) {
for (i = 0; i < COMMU_STR_MAX_LEN; i++)
string[i] = rtl8168_eri_read(ioaddr, Community + i, RW_ONE_BYTE, ERIAR_ASF);
} else { /* arg == ASF_SET */
for (i = 0; i < COMMU_STR_MAX_LEN; i++)
rtl8168_eri_write(ioaddr, Community + i, RW_ONE_BYTE, string[i], ERIAR_ASF);
}
}
void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
{
unsigned int value;
if (arg == ASF_GET) {
data[ASFCAPABILITY] = (rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF) & data[ASFCONFIG]) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
} else if (arg == ASF_SET) {
value = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
if (data[ASFCAPABILITY] == FUNCTION_ENABLE)
value |= data[ASFCONFIG];
else if (data[ASFCAPABILITY] == FUNCTION_DISABLE)
value &= ~data[ASFCONFIG];
rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, value, ERIAR_ASF);
}
}
void rtl8168_asf_console_mac(struct rtl8168_private *tp, int arg, unsigned int *data)
{
void __iomem *ioaddr=tp->mmio_addr;
int i;
if (arg == ASF_GET) {
for (i = 0; i < 6; i++)
data[i] = rtl8168_eri_read(ioaddr, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF);
} else if (arg == ASF_SET) {
for (i = 0; i < 6; i++)
rtl8168_eri_write(ioaddr, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
/* write the new console MAC address to EEPROM */
rtl_eeprom_write_sc(tp, 70, (data[1] << 8) | data[0]);
rtl_eeprom_write_sc(tp, 71, (data[3] << 8) | data[2]);
rtl_eeprom_write_sc(tp, 72, (data[5] << 8) | data[4]);
}
}
void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
{
int pos;
if (offset == WD8Rst)
pos = ASFWD8RESET;
else if (offset == LSnsrPollCycle)
pos = ASFLSNRPOLLCYC;
else if (offset == ASFSnsrPollPrd)
pos = ASFSNRPOLLCYC;
else if (offset == AlertReSendItvl)
pos = ASFALERTRESND;
if (arg == ASF_GET)
data[pos] = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
else /* arg == ASF_SET */
rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, data[pos], ERIAR_ASF);
}
void rtl8168_asf_ip_address(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
{
void __iomem *ioaddr=tp->mmio_addr;
int i;
int eeprom_off = 0;
if (arg == ASF_GET) {
for (i = 0; i < 4; i++)
data[i] = rtl8168_eri_read(ioaddr, offset + i, RW_ONE_BYTE, ERIAR_ASF);
} else if (arg == ASF_SET) {
for (i = 0; i < 4; i++)
rtl8168_eri_write(ioaddr, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
if (offset == ConsoleIP)
eeprom_off = 73;
else if (offset == IPAddr)
eeprom_off = 75;
/* write the new IP address to EEPROM */
rtl_eeprom_write_sc(tp, eeprom_off, (data[1] << 8) | data[0]);
rtl_eeprom_write_sc(tp, eeprom_off + 1, (data[3] << 8) | data[2]);
}
}
static int
OOB_set_ip_mac(struct rtl8168_private *tp, struct sockaddr_in *sa, u8 *mac)
{
u32 data;
if (tp->mcfg == CFG_METHOD_13) {
OCP_write(tp, 0xF, 0xd0, be32_to_cpu(sa->sin_addr.s_addr));
memcpy(&data, mac, 4);
OCP_write(tp, 0xF, 0x00, le32_to_cpu(data));
data = 0;
memcpy(&data, mac + 4, 2);
OCP_write(tp, 0x3, 0x04, le32_to_cpu(data));
OOB_notify(tp, OOB_CMD_SET_IPMAC);
} else if (tp->mcfg == CFG_METHOD_17) {
void __iomem *ioaddr = tp->mmio_addr;
struct net_device *dev = tp->dev;
u32 rx_mode;
rx_mode = RTL_R32(RxConfig);
if (netif_running(dev)) {
netif_stop_queue(dev);
RTL_W32(RxConfig, rx_mode & ~0x3f);
while ((RTL_R8(0xd3) & (BIT_5 | BIT_4)) != ((BIT_5 | BIT_4)))
udelay(20);
RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
// } else {
// unsigned long flags;
//
// spin_lock_irqsave(&tp->phy_lock, flags);
// mdio_write(tp, 0x1f, 0x0000);
// data = mdio_read(tp, MII_CTRL1000);
// data &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
// mdio_write(tp, MII_CTRL1000, data);
// mdio_write(tp, 0x00, 0x9200);
// spin_unlock_irqrestore(&tp->phy_lock, flags);
//
// ssleep(3);
// RTL_W16(IntrStatus, RTL_R16(IntrStatus));
//
// RTL_W32(MAR0, 0);
// RTL_W32(MAR0 + 4, 0);
// RTL_W16(RxMaxSize, 0x05f3);
}
RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7);
rtl8168_eri_write(ioaddr, 0x180, 4, 0x06080888, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x184, 4, 0xdd860008, ERIAR_ExGMAC);
memcpy(&data, mac, 2);
rtl8168_eri_write(ioaddr, 0xf0, 4, (le32_to_cpu(data) << 16), ERIAR_ExGMAC);
memcpy(&data, mac + 2, 4);
rtl8168_eri_write(ioaddr, 0xf4, 4, le32_to_cpu(data), ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x190, 4, 0x3c110600, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x194, 4, 0x2c32332b, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x198, 4, 0x003a0201, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x19c, 4, 0x00000000, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0x1f0, 4, cpu_to_le32(sa->sin_addr.s_addr), ERIAR_ExGMAC);
memcpy(&data, mac, 4);
rtl8168_eri_write(ioaddr, 0x258, 4, le32_to_cpu(data), ERIAR_ExGMAC);
memcpy(&data, mac + 4, 2);
rtl8168_eri_write(ioaddr, 0x25c, 2, le32_to_cpu(data), ERIAR_ExGMAC);
RTL_W8(0xe0, RTL_R8(0xe0) | BIT_6);
while (!(RTL_R8(0xd3) & BIT_1))
udelay(20);
RTL_W32(0xb0, 0x9800e035);
RTL_W32(0xb0, 0x9801e034);
RTL_W32(0xb0, 0x9802e019);
RTL_W32(0xb0, 0x98039918);
RTL_W32(0xb0, 0x9804c011);
RTL_W32(0xb0, 0x98057100);
RTL_W32(0xb0, 0x9806499f);
RTL_W32(0xb0, 0x9807f011);
RTL_W32(0xb0, 0x9808c00e);
RTL_W32(0xb0, 0x98097100);
RTL_W32(0xb0, 0x980A4995);
RTL_W32(0xb0, 0x980Bf00d);
RTL_W32(0xb0, 0x980C4895);
RTL_W32(0xb0, 0x980D9900);
RTL_W32(0xb0, 0x980Ec009);
RTL_W32(0xb0, 0x980F7100);
RTL_W32(0xb0, 0x98104890);
RTL_W32(0xb0, 0x98119900);
RTL_W32(0xb0, 0x98124810);
RTL_W32(0xb0, 0x98139900);
RTL_W32(0xb0, 0x9814e004);
RTL_W32(0xb0, 0x9815d44e);
RTL_W32(0xb0, 0x9816d506);
RTL_W32(0xb0, 0x9817c0b4);
RTL_W32(0xb0, 0x9818c002);
RTL_W32(0xb0, 0x9819b800);
RTL_W32(0xb0, 0x981A0500);
RTL_W32(0xb0, 0x981B1a26);
RTL_W32(0xb0, 0x981Ca4ca);
RTL_W32(0xb0, 0x981D21bc);
RTL_W32(0xb0, 0x981E25bc);
RTL_W32(0xb0, 0x981F1305);
RTL_W32(0xb0, 0x9820f00d);
RTL_W32(0xb0, 0x9821c213);
RTL_W32(0xb0, 0x98227340);
RTL_W32(0xb0, 0x982349b0);
RTL_W32(0xb0, 0x9824f009);
RTL_W32(0xb0, 0x98251a3a);
RTL_W32(0xb0, 0x9826a4ca);
RTL_W32(0xb0, 0x982721b9);
RTL_W32(0xb0, 0x982825b9);
RTL_W32(0xb0, 0x98291303);
RTL_W32(0xb0, 0x982Af006);
RTL_W32(0xb0, 0x982B1309);
RTL_W32(0xb0, 0x982Cf004);
RTL_W32(0xb0, 0x982Dc306);
RTL_W32(0xb0, 0x982E1a26);
RTL_W32(0xb0, 0x982Fbb00);
RTL_W32(0xb0, 0x9830c302);
RTL_W32(0xb0, 0x9831bb00);
RTL_W32(0xb0, 0x98320f3e);
RTL_W32(0xb0, 0x98330f4e);
RTL_W32(0xb0, 0x9834c0ae);
RTL_W32(0xb0, 0x98351800);
RTL_W32(0xb0, 0x9836b800);
RTL_W32(0xb0, 0xfe173000);
RTL_W32(0xb0, 0xfe1604ff);
RTL_W32(0xb0, 0xfe150f4d);
data = rtl8168_eri_read(ioaddr, 0xd6, 1, ERIAR_ExGMAC);
rtl8168_eri_write(ioaddr, 0xd6, 1, data | BIT_0, ERIAR_ExGMAC);
if (netif_running(dev)) {
rtl8168_init_ring_indexes(tp);
RTL_W8(ChipCmd, CmdRxEnb | CmdTxEnb);
RTL_W32(RxConfig, rx_mode);
netif_wake_queue(dev);
} else {
RTL_W8(0xD3, RTL_R8(0xD3) | BIT_7);
// data = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
// data &= ~BIT_0;
// rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC);
// data |= BIT_0;
// rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC);
RTL_W32(RxConfig, rx_mode | 0x0e);
}
} else {
return -EFAULT;
}
return 0;
}