u32 rtl92e_eeprom_read(struct net_device *dev, u32 addr) { struct r8192_priv *priv = rtllib_priv(dev); u32 ret = 0; rtl92e_writeb(dev, EPROM_CMD, (EPROM_CMD_PROGRAM << EPROM_CMD_OPERATING_MODE_SHIFT)); udelay(EPROM_DELAY); /* EEPROM is configured as x16 */ if (priv->epromtype == EEPROM_93C56) ret = _rtl92e_eeprom_xfer(dev, (addr & 0xFF) | (0x6 << 8), 11); else ret = _rtl92e_eeprom_xfer(dev, (addr & 0x3F) | (0x6 << 6), 9); rtl92e_writeb(dev, EPROM_CMD, (EPROM_CMD_NORMAL<<EPROM_CMD_OPERATING_MODE_SHIFT)); return ret; }
static void _rtl92e_gpio_write_bit(struct net_device *dev, int no, bool val) { u8 reg = rtl92e_readb(dev, EPROM_CMD); if (val) reg |= 1 << no; else reg &= ~(1 << no); rtl92e_writeb(dev, EPROM_CMD, reg); udelay(EPROM_DELAY); }
void rtl92e_set_rf_off(struct net_device *dev) { rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0); rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07); }
static bool _rtl92e_bb_config_para_file(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); bool rtStatus = true; u8 bRegValue = 0, eCheckItem = 0; u32 dwRegValue = 0; bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET); rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT)); dwRegValue = rtl92e_readl(dev, CPU_GEN); rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0; eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { rtStatus = rtl92e_check_bb_and_rf(dev, (enum hw90_block)eCheckItem, (enum rf90_radio_path)0); if (!rtStatus) { RT_TRACE((COMP_ERR | COMP_PHY), "rtl92e_config_rf():Check PHY%d Fail!!\n", eCheckItem-1); return rtStatus; } } rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG); dwRegValue = rtl92e_readl(dev, CPU_GEN); rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB); if (priv->IC_Cut > VERSION_8190_BD) { if (priv->rf_type == RF_2T4R) dwRegValue = (priv->AntennaTxPwDiff[2]<<8 | priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); else dwRegValue = 0x0; rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue); dwRegValue = priv->CrystalCap; rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); } return rtStatus; }
static bool _rtl92e_fw_boot_cpu(struct net_device *dev) { u32 CPU_status = 0; if (!_rtl92e_wait_for_fw(dev, CPU_GEN_PUT_CODE_OK, 200)) { netdev_err(dev, "Firmware download failed.\n"); return false; } netdev_dbg(dev, "Download Firmware: Put code ok!\n"); CPU_status = rtl92e_readl(dev, CPU_GEN); rtl92e_writeb(dev, CPU_GEN, (u8)((CPU_status|CPU_GEN_PWR_STB_CPU)&0xff)); mdelay(1); if (!_rtl92e_wait_for_fw(dev, CPU_GEN_BOOT_RDY, 200)) { netdev_err(dev, "Firmware boot failed.\n"); return false; } netdev_dbg(dev, "Download Firmware: Boot ready!\n"); return true; }
static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel, u8 *stage, u8 *step, u32 *delay) { struct r8192_priv *priv = rtllib_priv(dev); struct rtllib_device *ieee = priv->rtllib; u32 PreCommonCmdCnt; u32 PostCommonCmdCnt; u32 RfDependCmdCnt; struct sw_chnl_cmd *CurrentCmd = NULL; u8 eRFPath; RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel); if (!rtllib_legal_channel(priv->rtllib, channel)) { netdev_err(dev, "Invalid channel requested: %d\n", channel); return true; } { PreCommonCmdCnt = 0; _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, 0, 0, 0); _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); PostCommonCmdCnt = 0; _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); RfDependCmdCnt = 0; switch (priv->rf_chip) { case RF_8225: if (!(channel >= 1 && channel <= 14)) { netdev_err(dev, "Invalid channel requested for 8225: %d\n", channel); return false; } _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_End, 0, 0, 0); break; case RF_8256: if (!(channel >= 1 && channel <= 14)) { netdev_err(dev, "Invalid channel requested for 8256: %d\n", channel); return false; } _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_End, 0, 0, 0); break; case RF_8258: break; default: netdev_warn(dev, "Unknown RF Chip ID\n"); return false; } do { switch (*stage) { case 0: CurrentCmd = &ieee->PreCommonCmd[*step]; break; case 1: CurrentCmd = &ieee->RfDependCmd[*step]; break; case 2: CurrentCmd = &ieee->PostCommonCmd[*step]; break; } if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) { if ((*stage) == 2) return true; (*stage)++; (*step) = 0; continue; } if (!CurrentCmd) continue; switch (CurrentCmd->CmdID) { case CmdID_SetTxPowerLevel: if (priv->IC_Cut > (u8)VERSION_8190_BD) _rtl92e_set_tx_power_level(dev, channel); break; case CmdID_WritePortUlong: rtl92e_writel(dev, CurrentCmd->Para1, CurrentCmd->Para2); break; case CmdID_WritePortUshort: rtl92e_writew(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); break; case CmdID_WritePortUchar: rtl92e_writeb(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); break; case CmdID_RF_WriteReg: for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); break; default: break; } break; } while (true); } /*for (Number of RF paths)*/ (*delay) = CurrentCmd->msDelay; (*step)++; return false; }
static bool _rtl92e_set_rf_power_state(struct net_device *dev, enum rt_rf_power_state eRFPowerState) { struct r8192_priv *priv = rtllib_priv(dev); struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *) (&(priv->rtllib->PowerSaveControl)); bool bResult = true; u8 i = 0, QueueID = 0; struct rtl8192_tx_ring *ring = NULL; if (priv->SetRFPowerStateInProgress) return false; RT_TRACE(COMP_PS, "===========> _rtl92e_set_rf_power_state()!\n"); priv->SetRFPowerStateInProgress = true; switch (priv->rf_chip) { case RF_8256: switch (eRFPowerState) { case eRfOn: RT_TRACE(COMP_PS, "_rtl92e_set_rf_power_state() eRfOn!\n"); if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { bool rtstatus = true; u32 InitilizeCount = 3; do { InitilizeCount--; priv->RegRfOff = false; rtstatus = rtl92e_enable_nic(dev); } while (!rtstatus && (InitilizeCount > 0)); if (!rtstatus) { netdev_err(dev, "%s(): Failed to initialize Adapter.\n", __func__); priv->SetRFPowerStateInProgress = false; return false; } RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else { rtl92e_writeb(dev, ANAPAR, 0x37); mdelay(1); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); priv->bHwRfOffAction = 0; rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); } break; case eRfSleep: if (priv->rtllib->eRFPowerState == eRfOff) break; for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { ring = &priv->tx_ring[QueueID]; if (skb_queue_len(&ring->queue) == 0) { QueueID++; continue; } else { RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if (i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! _rtl92e_set_rf_power_state(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } rtl92e_set_rf_off(dev); break; case eRfOff: RT_TRACE(COMP_PS, "_rtl92e_set_rf_power_state() eRfOff/Sleep !\n"); for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) { ring = &priv->tx_ring[QueueID]; if (skb_queue_len(&ring->queue) == 0) { QueueID++; continue; } else { RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); udelay(10); i++; } if (i >= MAX_DOZE_WAITING_TIMES_9x) { RT_TRACE(COMP_POWER, "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n", MAX_DOZE_WAITING_TIMES_9x, QueueID); break; } } if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) { rtl92e_disable_nic(dev); RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); } else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC)) { rtl92e_set_rf_off(dev); } break; default: bResult = false; netdev_warn(dev, "%s(): Unknown state requested: 0x%X.\n", __func__, eRFPowerState); break; } break; default: netdev_warn(dev, "%s(): Unknown RF type\n", __func__); break; } if (bResult) { priv->rtllib->eRFPowerState = eRFPowerState; switch (priv->rf_chip) { case RF_8256: break; default: netdev_warn(dev, "%s(): Unknown RF type\n", __func__); break; } } priv->SetRFPowerStateInProgress = false; RT_TRACE(COMP_PS, "<=========== _rtl92e_set_rf_power_state() bResult = %d!\n", bResult); return bResult; }
void rtl92e_init_gain(struct net_device *dev, u8 Operation) { #define SCAN_RX_INITIAL_GAIN 0x17 #define POWER_DETECTION_TH 0x08 struct r8192_priv *priv = rtllib_priv(dev); u32 BitMask; u8 initial_gain; if (priv->up) { switch (Operation) { case IG_Backup: RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); initial_gain = SCAN_RX_INITIAL_GAIN; BitMask = bMaskByte0; if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); priv->initgain_backup.xaagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask); priv->initgain_backup.xbagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask); priv->initgain_backup.xcagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask); priv->initgain_backup.xdagccore1 = (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask); BitMask = bMaskByte2; priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev, rCCK0_CCA, BitMask); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", initial_gain); rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain); rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain); rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain); rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain); RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", POWER_DETECTION_TH); rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH); break; case IG_Restore: RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); BitMask = 0x7f; if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8); rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); BitMask = bMaskByte2; rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1); RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca); rtl92e_set_tx_power(dev, priv->rtllib->current_network.channel); if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1); break; default: RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); break; } } }
static void _rtl92e_set_bw_mode_work_item(struct net_device *dev) { struct r8192_priv *priv = rtllib_priv(dev); u8 regBwOpMode; RT_TRACE(COMP_SWBW, "==>_rtl92e_set_bw_mode_work_item() Switch to %s bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ? "20MHz" : "40MHz"); if (priv->rf_chip == RF_PSEUDO_11N) { priv->SetBWModeInProgress = false; return; } if (!priv->up) { netdev_err(dev, "%s(): Driver is not initialized\n", __func__); return; } regBwOpMode = rtl92e_readb(dev, BW_OPMODE); switch (priv->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ; rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); break; case HT_CHANNEL_WIDTH_20_40: regBwOpMode &= ~BW_OPMODE_20MHZ; rtl92e_writeb(dev, BW_OPMODE, regBwOpMode); break; default: netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, priv->CurrentChannelBW); break; } switch (priv->CurrentChannelBW) { case HT_CHANNEL_WIDTH_20: rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); if (!priv->btxpower_tracking) { rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000); rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317); rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204); } else { _rtl92e_cck_tx_power_track_bw_switch(dev); } rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); break; case HT_CHANNEL_WIDTH_20_40: rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); if (!priv->btxpower_tracking) { rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000); rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e); rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409); } else { _rtl92e_cck_tx_power_track_bw_switch(dev); } rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); break; default: netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__, priv->CurrentChannelBW); break; } switch (priv->rf_chip) { case RF_8225: break; case RF_8256: rtl92e_set_bandwidth(dev, priv->CurrentChannelBW); break; case RF_8258: break; case RF_PSEUDO_11N: break; default: netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__, priv->rf_chip); break; } atomic_dec(&(priv->rtllib->atm_swbw)); priv->SetBWModeInProgress = false; RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); }
static int r8192_wx_set_enc_ext(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra) { int ret = 0; struct r8192_priv *priv = rtllib_priv(dev); struct rtllib_device *ieee = priv->rtllib; if (priv->bHwRadioOff) return 0; down(&priv->wx_sem); priv->rtllib->wx_set_enc = 1; down(&priv->rtllib->ips_sem); rtl92e_ips_leave(dev); up(&priv->rtllib->ips_sem); ret = rtllib_wx_set_encode_ext(ieee, info, wrqu, extra); { const u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; const u8 zero[ETH_ALEN] = {0}; u32 key[4] = {0}; struct iw_encode_ext *ext = (struct iw_encode_ext *)extra; struct iw_point *encoding = &wrqu->encoding; u8 idx = 0, alg = 0, group = 0; if ((encoding->flags & IW_ENCODE_DISABLED) || ext->alg == IW_ENCODE_ALG_NONE) { ieee->pairwise_key_type = ieee->group_key_type = KEY_TYPE_NA; rtl92e_cam_reset(dev); memset(priv->rtllib->swcamtable, 0, sizeof(struct sw_cam_table) * 32); goto end_hw_sec; } alg = (ext->alg == IW_ENCODE_ALG_CCMP) ? KEY_TYPE_CCMP : ext->alg; idx = encoding->flags & IW_ENCODE_INDEX; if (idx) idx--; group = ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY; if ((!group) || (IW_MODE_ADHOC == ieee->iw_mode) || (alg == KEY_TYPE_WEP40)) { if ((ext->key_len == 13) && (alg == KEY_TYPE_WEP40)) alg = KEY_TYPE_WEP104; ieee->pairwise_key_type = alg; rtl92e_enable_hw_security_config(dev); } memcpy((u8 *)key, ext->key, 16); if ((alg & KEY_TYPE_WEP40) && (ieee->auth_mode != 2)) { if (ext->key_len == 13) ieee->pairwise_key_type = alg = KEY_TYPE_WEP104; rtl92e_set_key(dev, idx, idx, alg, zero, 0, key); rtl92e_set_swcam(dev, idx, idx, alg, zero, 0, key, 0); } else if (group) { ieee->group_key_type = alg; rtl92e_set_key(dev, idx, idx, alg, broadcast_addr, 0, key); rtl92e_set_swcam(dev, idx, idx, alg, broadcast_addr, 0, key, 0); } else { if ((ieee->pairwise_key_type == KEY_TYPE_CCMP) && ieee->pHTInfo->bCurrentHTSupport) rtl92e_writeb(dev, 0x173, 1); rtl92e_set_key(dev, 4, idx, alg, (u8 *)ieee->ap_mac_addr, 0, key); rtl92e_set_swcam(dev, 4, idx, alg, (u8 *)ieee->ap_mac_addr, 0, key, 0); } } end_hw_sec: priv->rtllib->wx_set_enc = 0; up(&priv->wx_sem); return ret; }