示例#1
0
static inline int
s3c_serial_setsource(struct uart_port *port, struct s3c_uart_clksrc *c)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);

	return (info->set_clksrc)(port, c);
}
示例#2
0
static inline int s3c_serial_resetport(struct uart_port *port,
					   struct s3c_uartcfg *cfg)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);

	return (info->reset_port)(port, cfg);
}
示例#3
0
static void s3c_serial_config_port(struct uart_port *port, int flags)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);

	if (flags & UART_CONFIG_TYPE && s3c_serial_request_port(port) == 0)
		port->type = info->type;
}
示例#4
0
/*
 * verify the new serial_struct (for TIOCSSERIAL).
 */
static int
s3c_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);

	if (ser->type != PORT_UNKNOWN && ser->type != info->type)
		return -EINVAL;

	return 0;
}
示例#5
0
static unsigned int s3c_serial_tx_empty(struct uart_port *port)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);
	unsigned long ufstat = rd_regl(port, S3C_UFSTAT);
	unsigned long ufcon = rd_regl(port, S3C_UFCON);

	if (ufcon & S3C_UFCON_FIFOMODE) {
		if ((ufstat & info->tx_fifomask) != 0 ||
		    (ufstat & info->tx_fifofull))
			return 0;

		return 1;
	}

	return s3c_serial_txempty_nofifo(port);
}
示例#6
0
static int
s3c_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
{
	struct s3c_uart_info *info = s3c_port_to_info(port);
	unsigned long ufstat, utrstat;

	if (ufcon & S3C_UFCON_FIFOMODE) {
		/* fifo mode - check ammount of data in fifo registers... */
		ufstat = rd_regl(port, S3C_UFSTAT);
		return (ufstat & info->tx_fifofull) ? 0 : 1;
	}

	/* in non-fifo mode, we go and use the tx buffer empty */
	utrstat = rd_regl(port, S3C_UTRSTAT);
	return (utrstat & S3C_UTRSTAT_TXE) ? 1 : 0;
}
示例#7
0
static int s3c_serial_resetport(struct uart_port *port,
				    struct s3c2410_uartcfg *cfg)
{
#if 0
	struct s3c_uart_info *info = s3c_port_to_info(port);

	return (info->reset_port)(port, cfg);
#else
	/* ensure registers are setup */
	dbg("s3c_serial_resetport: port=%p (%08lx), cfg=%p\n",
	    port, port->mapbase, cfg);

	wr_regl(port, S3C_UCON,  cfg->ucon);
	wr_regl(port, S3C_ULCON, cfg->ulcon);

	/* reset both fifos */
	wr_regl(port, S3C_UFCON, cfg->ufcon | S3C_UFCON_RESETBOTH);
	wr_regl(port, S3C_UFCON, cfg->ufcon);

	return 0;

#endif
}