void __init_or_cpufreq s5p6440_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
unsigned int ptr;
/* */
clk_fout_epll.enable = s5p_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops;
clk_48m.enable = s5p64x0_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
__raw_readl(S5P64X0_EPLL_CON_K));
clk_fout_apll.rate = apll;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk.clk);
pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
pclk_low = clk_get_rate(&clk_pclk_low.clk);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long apll;
unsigned long mpll;
unsigned long epll;
u32 clkdiv0, clkdiv1;
struct clk *clk_mmc;
clk_fout_epll.enable = s5pv210_epll_enable;
clk_fout_epll.ops = &s5pv210_epll_ops;
clk_fout_vpll.enable = s5pv210_vpll_enable;
clk_fout_vpll.ops = &s5pv210_vpll_ops;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
clkdiv1 = __raw_readl(S5P_CLK_DIV1);
printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
__func__, clkdiv0, clkdiv1);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
__raw_readl(S5P_EPLL_CON_K));
printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
clk_fout_apll.ops = &s5pv210_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_f.rate = clk_get_rate(&clk_armclk.clk);
clk_h.rate = clk_get_rate(&clk_hclk_133.clk);
clk_p.rate = clk_get_rate(&clk_pclk_66.clk);
clk_set_parent(&clk_mout_mmc0.clk, &clk_mout_mpll.clk);
clk_set_parent(&clk_mout_mmc1.clk, &clk_mout_mpll.clk);
clk_set_parent(&clk_mout_mmc2.clk, &clk_mout_mpll.clk);
clk_set_parent(&clk_mout_mmc3.clk, &clk_mout_mpll.clk);
clk_set_rate(&clk_sclk_mmc0.clk, 50*MHZ);
clk_set_rate(&clk_sclk_mmc1.clk, 50*MHZ);
clk_set_rate(&clk_sclk_mmc2.clk, 50*MHZ);
clk_set_rate(&clk_sclk_mmc3.clk, 50*MHZ);
}
void __init_or_cpufreq s5p6450_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk_low;
unsigned long pclk;
unsigned long pclk_low;
unsigned long epll;
unsigned long dpll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
/* Set S5P6450 functions for clk_fout_epll */
clk_fout_epll.enable = s5p6450_epll_enable;
clk_fout_epll.ops = &s5p6450_epll_ops;
clk_48m.enable = s5p6450_clk48m_ctrl;
xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
__raw_readl(S5P_EPLL_CON_K));
dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P_DPLL_CON),
__raw_readl(S5P_DPLL_CON_K), pll_4650c);
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_dpll.rate = dpll;
clk_fout_apll.rate = apll;
ctable.apll_rate = clk_fout_apll.rate/1000000;
switch (ctable.apll_rate)
{
case IS_ARM_800 :
ctable.clock_table_size = ARRAY_SIZE(clock_table_800);
ctable.clock_table = clock_table_800;
break;
case IS_ARM_667:
ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
ctable.clock_table = clock_table_667;
break;
case IS_ARM_533:
ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
ctable.clock_table = clock_table_533;
break;
default:
printk("------------------------- UNKNOW FREQ WARNING !!!!!!!!!--------------- e \n");
}
/*
if(ctable.apll_rate == IS_ARM_667){
printk("----------------------------------------- 667 Freq table \n");
ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
ctable.clock_table = clock_table_667;
}else if(ctable.apll_rate == IS_ARM_533)
{
printk("----------------------------------------- 533 Freq table \n");
ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
ctable.clock_table = clock_table_533;
}
*/
printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(dpll));
fclk = clk_get_rate(&clk_armclk.clk);
hclk = clk_get_rate(&clk_hclk166.clk);
pclk = clk_get_rate(&clk_pclk83.clk);
hclk_low = clk_get_rate(&clk_hclk133.clk);
pclk_low = clk_get_rate(&clk_pclk66.clk);
printk(KERN_INFO "S5P6450: HCLK166=%ld.%ldMHz, HCLK133=%ld.%ldMHz," \
" PCLK83=%ld.%ldMHz, PCLK66=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low));
clk_f.rate = fclk;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_h_low.rate = hclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
s3c_set_clksrc(clksrc_audio + ptr, true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
