static void __init sherman_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static void __init cep_map_io(void)
{
sa1100_map_io();
iotable_init(cep_io_desc);
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(2, 3); /* radio module */
/*
* Ensure that these pins are set as outputs and are driving
* logic 0. This ensures that we won't inadvertently toggle
* the WS latch in the CPLD, and we don't float causing
* excessive power drain. --rmk
*/
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0;
PGSR = 0;
PCFR = 0;
PSDR = 0;
}
static void __init victor_map_io(void)
{
sa1100_map_io();
iotable_init(victor_io_desc);
sa1100_register_uart(0, 3);
}
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
GAFR |= GPIO_UART_TXD | GPIO_UART_RXD;
GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
PWER = PWER_GPIO0| PWER_RTC;
PGSR = 0x818;
PCFR = 0;
PSDR = 0;
sa11x0_set_flash_data(&simpad_flash_data, simpad_flash_resources,
ARRAY_SIZE(simpad_flash_resources));
sa11x0_set_mcp_data(&simpad_mcp_data);
}
static void __init pleb_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Fix expansion memory timing for network card
*/
MECR = ((2<<10) | (2<<5) | (2<<0));
/*
* Enable the SMC ethernet controller
*/
GPDR |= GPIO_ETH0_EN; /* set to output */
GPCR = GPIO_ETH0_EN; /* clear MCLK (enable smc) */
GPDR &= ~GPIO_ETH0_IRQ;
set_irq_type(GPIO_ETH0_IRQ, IRQT_FALLING);
}
static void __init assabet_map_io(void)
{
sa1100_map_io();
iotable_init(assabet_io_desc, ARRAY_SIZE(assabet_io_desc));
/*
* Set SUS bit in SDCR0 so serial port 1 functions.
* Its called GPCLKR0 in my SA1110 manual.
*/
Ser1SDCR0 |= SDCR0_SUS;
MSC1 = (MSC1 & ~0xffff) |
MSC_NonBrst | MSC_32BitStMem |
MSC_RdAcc(2) | MSC_WrAcc(2) | MSC_Rec(0);
if (!machine_has_neponset())
sa1100_register_uart_fns(&assabet_port_fns);
/*
* When Neponset is attached, the first UART should be
* UART3. That's what Angel is doing and many documents
* are stating this.
*
* We do the Neponset mapping even if Neponset support
* isn't compiled in so the user will still get something on
* the expected physical serial port.
*
* We no longer do this; not all boot loaders support it,
* and UART3 appears to be somewhat unreliable with blob.
*/
sa1100_register_uart(0, 1);
sa1100_register_uart(2, 3);
}
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3); /* serial interface */
sa1100_register_uart(1, 1); /* DECT */
// Reassign UART 1 pins
GAFR |= GPIO_UART_TXD | GPIO_UART_RXD;
GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0| PWER_RTC;
PGSR = 0x818;
PCFR = 0;
PSDR = 0;
}
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON |
RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
__simpad_write_cs3();
sa1100_register_uart_fns(&simpad_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
GAFR |= GPIO_UART_TXD | GPIO_UART_RXD;
GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
PWER = PWER_GPIO0| PWER_RTC;
PGSR = 0x818;
PCFR = 0;
PSDR = 0;
}
static void __init h3600_map_io(void)
{
sa1100_map_io();
iotable_init(h3600_io_desc);
sa1100_register_uart_fns(&h3600_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1); /* isn't this one driven elsewhere? */
/*
* Default GPIO settings. Should be set by machine
*/
GPCR = 0x0fffffff;
// GPDR = 0x0401f3fc;
GPDR = GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK |
GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA |
GPIO_H3600_CLK_SET1 | GPIO_H3600_CLK_SET0 |
GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 |
GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
init_h3600_egpio();
/*
* Ensure those pins are outputs and driving low.
*/
PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
/* Configure suspend conditions */
PGSR = 0;
PWER = PWER_GPIO0 | PWER_RTC;
PCFR = PCFR_OPDE;
PSDR = 0;
}
static void __init jornada720_map_io(void)
{
sa1100_map_io();
iotable_init(jornada720_io_desc);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static void __init xp860_map_io(void)
{
sa1100_map_io();
iotable_init(xp860_io_desc, ARRAY_SIZE(xp860_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static void __init badge4_map_io(void)
{
sa1100_map_io();
iotable_init(badge4_io_desc, ARRAY_SIZE(badge4_io_desc));
sa1100_register_uart_fns(&badge4_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static void __init yopy_map_io(void)
{
sa1100_map_io();
iotable_init(yopy_io_desc);
sa1100_register_uart(0, 3);
set_GPIO_IRQ_edge(GPIO_UCB1200_IRQ, GPIO_RISING_EDGE);
}
static void __init assabet_map_io(void)
{
extern void neponset_map_io(void);
sa1100_map_io();
iotable_init(assabet_io_desc);
#ifdef CONFIG_ASSABET_NEPONSET
/*
* We map Neponset registers even if it isn't present since
* many drivers will try to probe their stuff (and fail).
* This is still more friendly than a kernel paging request
* crash.
*/
neponset_map_io();
#endif
if (machine_has_neponset()) {
/*
* When Neponset is attached, the first UART should be
* UART3. That's what Angel is doing and many documents
* are stating this.
* We do the Neponset mapping even if Neponset support
* isn't compiled in so the user will still get something on
* the expected physical serial port.
*/
sa1100_register_uart(0, 3);
sa1100_register_uart(2, 1);
/*
* Set SUS bit in SDCR0 so serial port 1 functions.
* Its called GPCLKR0 in my SA1110 manual.
*/
Ser1SDCR0 |= SDCR0_SUS;
} else {
sa1100_register_uart_fns(&assabet_port_fns);
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(2, 3); /* radio module */
}
/*
* Ensure that these pins are set as outputs and are driving
* logic 0. This ensures that we won't inadvertently toggle
* the WS latch in the CPLD, and we don't float causing
* excessive power drain. --rmk
*/
GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
/*
* Set up registers for sleep mode.
*/
PWER = PWER_GPIO0;
PGSR = 0;
PCFR = 0;
PSDR = 0;
}
static void __init empeg_map_io(void)
{
sa1100_map_io();
iotable_init(empeg_io_desc, ARRAY_SIZE(empeg_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 3);
sa1100_register_uart(2, 2);
Ser1SDCR0 |= SDCR0_UART;
}
static void __init brutus_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 3);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
}
static void __init collie_map_io(void)
{
sa1100_map_io();
iotable_init(collie_io_desc, ARRAY_SIZE(collie_io_desc));
#ifdef CONFIG_SHARP_LOCOMO
sa1100_register_uart_fns(&collie_port_fns);
#endif
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
}
static void __init cerf_map_io(void)
{
sa1100_map_io();
iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 1);
GPDR |= CERF_GPIO_CF_RESET;
}
static void __init hackkit_map_io(void)
{
sa1100_map_io();
iotable_init(hackkit_io_desc, ARRAY_SIZE(hackkit_io_desc));
sa1100_register_uart_fns(&hackkit_port_fns);
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 3); /* radio module */
Ser1SDCR0 |= SDCR0_SUS;
}
static void __init adsbitsy_map_io(void)
{
sa1100_map_io();
iotable_init(adsbitsy_io_desc, ARRAY_SIZE(adsbitsy_io_desc));
sa1100_register_uart_fns(&adsbitsy_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18);
}
static void __init cerf_map_io(void)
{
sa1100_map_io();
iotable_init(cerf_io_desc, ARRAY_SIZE(cerf_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 2); /* disable this and the uart2 device for sa1100_fir */
sa1100_register_uart(2, 1);
/* set some GPDR bits here while it's safe */
GPDR |= CERF_GPIO_CF_RESET;
}
static void __init nanoengine_map_io(void)
{
sa1100_map_io();
iotable_init(nanoengine_io_desc, ARRAY_SIZE(nanoengine_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 3);
Ser1SDCR0 |= SDCR0_UART;
/* disable IRDA -- UART2 is used as a normal serial port */
Ser2UTCR4 = 0;
Ser2HSCR0 = 0;
}
static void __init system3_map_io(void)
{
DPRINTK( "%s\n", "START" );
sa1100_map_io();
iotable_init(system3_io_desc);
sa1100_register_uart_fns(&system3_port_fns);
sa1100_register_uart(0, 1); /* com port */
sa1100_register_uart(1, 2);
sa1100_register_uart(2, 3); /* radio module */
Ser1SDCR0 |= SDCR0_SUS;
}
static void __init frodo_map_io (void)
{
sa1100_map_io ();
iotable_init (frodo_io_desc);
sa1100_register_uart (0,2); /* UART2 (serial console) */
sa1100_register_uart (1,1); /* UART1 (big kahuna flow control serial port) */
/*
* Set SUS bit in SDCR0 so serial port 1 acts as a UART.
* See Intel SA-1110 Developers Manual Section 11.9.2.1 (GPCLK/UART Select)
*/
Ser1SDCR0 |= SDCR0_SUS;
}
static void __init graphicsmaster_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsmaster_io_desc);
sa1100_register_uart_fns(&graphicsmaster_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
/* set GPDR now */
GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18);
}
static void __init lart_map_io(void)
{
sa1100_map_io();
iotable_init(lart_io_desc, ARRAY_SIZE(lart_io_desc));
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
sa1100_register_uart(2, 2);
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
}
static void __init pangolin_map_io(void)
{
sa1100_map_io();
iotable_init(pangolin_io_desc, ARRAY_SIZE(pangolin_io_desc));
sa1100_register_uart(0, 1);
sa1100_register_uart(1, 3);
Ser1SDCR0 |= SDCR0_UART;
/* set some GPDR bits while it's safe */
GPDR |= GPIO_PCMCIA_RESET;
#ifndef CONFIG_SA1100_PANGOLIN_PCMCIA_IDE
GPDR |= GPIO_PCMCIA_BUS_ON;
#endif
}
static void __init shannon_map_io(void)
{
sa1100_map_io();
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
Ser1SDCR0 |= SDCR0_SUS;
GAFR |= (GPIO_UART_TXD | GPIO_UART_RXD);
GPDR |= GPIO_UART_TXD | SHANNON_GPIO_CODEC_RESET;
GPDR &= ~GPIO_UART_RXD;
PPAR |= PPAR_UPR;
/* reset the codec */
GPCR = SHANNON_GPIO_CODEC_RESET;
GPSR = SHANNON_GPIO_CODEC_RESET;
}
static void __init simpad_map_io(void)
{
sa1100_map_io();
iotable_init(simpad_io_desc);
PSPR = 0xc0008000;
GPDR &= ~GPIO_GPIO0;
cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
ENABLE_5V | RESET_SIMCARD);
*(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
//It is only possible to register 3 UART in serial_sa1100.c
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
set_GPIO_IRQ_edge(GPIO_UCB1300_IRQ);
}
static void __init graphicsmaster_map_io(void)
{
sa1100_map_io();
iotable_init(graphicsmaster_io_desc);
sa1100_register_uart_fns(&graphicsmaster_port_fns);
sa1100_register_uart(0, 3);
sa1100_register_uart(1, 1);
// don't register if you want to use IRDA
#ifndef CONFIG_SA1100_FIR
sa1100_register_uart(2, 2);
#endif
/* set GPDR now */
GPDR |= GPIO_GPIO15 | GPIO_GPIO17 | GPIO_GPIO19;
GPDR &= ~(GPIO_GPIO14 | GPIO_GPIO16 | GPIO_GPIO18);
}