void __start(void) { const uint32_t *src; uint32_t *dest; /* Configure the uart so that we can get debug output as soon as possible */ sam_clockconfig(); sam_lowsetup(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ for (dest = &_sbss; dest < &_ebss; ) { *dest++ = 0; } showprogress('B'); /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the * end of all of the other read-only data (.text, .rodata) at _eronly. */ for (src = &_eronly, dest = &_sdata; dest < &_edata; ) { *dest++ = *src++; } showprogress('C'); /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); #endif showprogress('D'); /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. * Normally this just means initializing the user space .data and .bss * segments. */ #ifdef CONFIG_NUTTX_KERNEL sam_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ sam_boardinitialize(); showprogress('F'); /* Then start NuttX */ showprogress('\r'); showprogress('\n'); os_start(); /* Shoulnd't get here */ for (;;); }
void up_boot(void) { #ifdef CONFIG_ARCH_RAMFUNCS const uint32_t *src; uint32_t *dest; #endif #ifndef CONFIG_ARCH_ROMPGTABLE /* __start provided the basic MMU mappings for SRAM. Now provide mappings * for all IO regions (Including the vector region). */ sam_setupmappings(); /* Provide a special mapping for the IRAM interrupt vector positioned in * high memory. */ sam_vectormapping(); #endif /* CONFIG_ARCH_ROMPGTABLE */ #ifdef CONFIG_ARCH_RAMFUNCS /* Copy any necessary code sections from FLASH to RAM. The correct * destination in SRAM is given by _sramfuncs and _eramfuncs. The * temporary location is in flash after the data initialization code * at _framfuncs */ for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) { *dest++ = *src++; } /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) #endif /* Setup up vector block. _vector_start and _vector_end are exported from * arm_vector.S */ sam_copyvectorblock(); /* Disable the watchdog timer */ sam_wdtdisable(); /* Initialize clocking to settings provided by board-specific logic */ sam_clockconfig(); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); #endif /* Perform board-specific initialization, This must include: * * - Initialization of board-specific memory resources (e.g., SDRAM) * - Configuration of board specific resources (PIOs, LEDs, etc). * * NOTE: We must use caution prior to this point to make sure that * the logic does not access any global variables that might lie * in SDRAM. */ sam_boardinitialize(); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level * initialization. Now that the SDRAM has been fully initialized, * we can reconfigure the SDRAM in its final, fully cache-able state. */ sam_remap(); #endif #ifdef CONFIG_BOOT_SDRAM_DATA /* If .data and .bss reside in SDRAM, then initialize the data sections * now after SDRAM has been initialized. */ arm_data_initialize(); #endif /* Perform common, low-level chip initialization (might do nothing) */ sam_lowsetup(); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial * driver. */ sam_earlyserialinit(); #endif }
void __start(void) { const uint32_t *src; uint32_t *dest; /* Clear .bss. We'll do this inline (vs. calling memset) just to be * certain that there are no issues with the state of global variables. */ for (dest = &_sbss; dest < &_ebss; ) { *dest++ = 0; } /* Move the initialized data section from his temporary holding spot in * FLASH into the correct place in SRAM. The correct place in SRAM is * give by _sdata and _edata. The temporary location is in FLASH at the * end of all of the other read-only data (.text, .rodata) at _eronly. */ for (src = &_eronly, dest = &_sdata; dest < &_edata; ) { *dest++ = *src++; } #ifdef NEED_WDT_DISABLE /* Disable the watchdog timer */ # warning Missing logic #endif /* Copy any necessary code sections from FLASH to RAM. The correct * destination in SRAM is geive by _sramfuncs and _eramfuncs. The * temporary location is in flash after the data initalization code * at _framfuncs. This must be done before sam_clockconfig() can be * called (at least for the SAM4L family). */ #ifdef CONFIG_ARCH_RAMFUNCS for (src = &_framfuncs, dest = &_sramfuncs; dest < &_eramfuncs; ) { *dest++ = *src++; } #endif /* Configure the uart so that we can get debug output as soon as possible */ sam_clockconfig(); sam_lowsetup(); showprogress('A'); /* Perform early serial initialization */ #ifdef USE_EARLYSERIALINIT up_earlyserialinit(); #endif showprogress('B'); /* For the case of the separate user-/kernel-space build, perform whatever * platform specific initialization of the user memory is required. * Normally this just means initializing the user space .data and .bss * segements. */ #ifdef CONFIG_NUTTX_KERNEL sam_userspace(); showprogress('C'); #endif /* Initialize onboard resources */ sam_boardinitialize(); showprogress('D'); /* Then start NuttX */ showprogress('\r'); showprogress('\n'); os_start(); /* Shouldn't get here */ for(;;); }