示例#1
0
void save_pm_secure_mem_status(volatile __u32 val)
{
	save_mem_status(val);
	return;
}
示例#2
0
/*
*********************************************************************************************************
*                           mem_power_init
*
* Description: init power for mem.
*
* Arguments  : none;
*
* Returns    : 0: succeed;
*			 -1: failed;
*********************************************************************************************************
*/
__s32 mem_power_init(__u32 wakeup_src)
{
	__u8 reg_val;
	
	save_mem_status(TWI_TRANSFER_STATUS );
	/* enable power key long/short */
	if(wakeup_src & AXP_WAKEUP_KEY){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, &reg_val)){
				return -1;
			}
			reg_val |= 0x03;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, &reg_val) ){
				return -1;
			}
	}

	/*enable power key short: bit1*/
	if(wakeup_src & AXP_WAKEUP_SHORT_KEY){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, &reg_val)){
				return -1;
			}
			reg_val |= 0x02;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, &reg_val) ){
				return -1;
			}
	}

	/*enable power key long: bit0*/
	if(wakeup_src & AXP_WAKEUP_LONG_KEY){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN3, &reg_val)){
				return -1;
			}
			reg_val |= 0x01;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN3, &reg_val) ){
				return -1;
			}
	}	

	/*°Ñ44H¼Ä´æÆ÷µÄbit6(°´¼üÉÏÉýÑØ´¥·¢)ÖÃ1*/
	if(wakeup_src & AXP_WAKEUP_ASCEND){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN5, &reg_val)){
				return -1;
			}
			reg_val |= 0x40;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN5, &reg_val)){
				return -1;
			}
	}
	
	/*°Ñ44H¼Ä´æÆ÷µÄbit5(ϽµÑØ´¥·¢)ÖÃ1*/
	if(wakeup_src & AXP_WAKEUP_DESCEND){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN5, &reg_val)){
				return -1;
			}
			reg_val |= 0x20;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN5, &reg_val)){
				return -1;
			}
	}
	
	/* enable low voltage warning */
	if(wakeup_src & AXP_WAKEUP_LOWBATT){
			if(twi_byte_rw(TWI_OP_RD, AXP_ADDR,AXP20_IRQEN4, &reg_val)){
				return -1;
			}
			reg_val |= 0x03;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQEN4, &reg_val)){
				return -1;
			}

			/* clear pending */
			reg_val = 0x03;
			if(twi_byte_rw(TWI_OP_WR, AXP_ADDR,AXP20_IRQ4, &reg_val)){
				return -1;
			}
	}
		
	return 0;
}