C++ (Cpp) sbPcieGppLateInit示例

示例#1

文件： SBMAIN.c 项目： bandwidthcrunch/coreboot

/**
 *  sbLatePost - Prepare Southbridge to boot to OS.
 *
 *
 *
 * @param[in] pConfig Southbridge configuration structure pointer.
 *
 */
VOID
sbLatePost (
  IN       AMDSBCFG* pConfig
  )
{
// UINT16 dwVar;
  BUILDPARAM  *pStaticOptions;
  pStaticOptions = &(pConfig->BuildParameters);
  commonInitLateBoot (pConfig);
  sataInitLatePost (pConfig);
  gecInitLatePost (pConfig);
  hpetInit (pConfig, pStaticOptions);                 // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
  ecInitLatePost (pConfig);
#endif
  sbPcieGppLateInit (pConfig);

}

示例#2

文件： SbMain.c 项目： bandwidthcrunch/coreboot

/**
 *  sbLatePost - Prepare Southbridge to boot to OS.
 *
 *
 *
 * @param[in] pConfig Southbridge configuration structure pointer.
 *
 */
VOID
sbLatePost (
  IN       AMDSBCFG* pConfig
  )
{
// UINT16 dwVar;
  BUILDPARAM  *pStaticOptions;
  pStaticOptions = &(pConfig->BuildParameters);
  TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
  commonInitLateBoot (pConfig);
  sataInitLatePost (pConfig);
  gecInitLatePost (pConfig);
  hpetInit (pConfig, pStaticOptions);                 // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
  ecInitLatePost (pConfig);
#endif
  sbPcieGppLateInit (pConfig);
  hwmImcInit (pConfig);
//  hwmSbtsiAutoPollingOff (pConfig);
  imcDisarmSurebootTimer (pConfig);
  usbInitLate (pConfig);                      // Init USB
  StressResetModeLate (pConfig);                      //
}

示例#3

static void pcie_init(device_t dev)
{
	sbPcieGppLateInit(sb_config);
}