void
si_core_disable(si_t *sih, uint32 bits)
{
if (CHIPTYPE(sih->socitype) == SOCI_SB)
sb_core_disable(sih, bits);
else if (CHIPTYPE(sih->socitype) == SOCI_AI)
ai_core_disable(sih, bits);
}
static void __init pcibios_fixup_resources(struct pci_dev *dev)
{
ulong flags;
uint coreidx;
if (dev->bus->number == 0) {
/*
* Chipcommon, RAM controller and PCI bridge must not be reset!
*/
if (dev->device == SB_MIPS ||
dev->device == SB_MIPS33 ||
dev->device == SB_EXTIF ||
dev->device == SB_MEMC ||
dev->device == SB_PCI || dev->device == SB_CC)
return;
spin_lock_irqsave(&sbh_lock, flags);
coreidx = sb_coreidx(sbh);
if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
return;
/*
* The USB core requires a special bit to be set during core
* reset to enable host (OHCI) mode. Resetting the SB core here
* is a hack for compatibility with vanilla usb-ohci so that it
* does not have to know about SB. A driver that wants to use
* the USB core in device mode should know about SB and should
* reset the bit back to 0.
*/
if (sb_coreid(sbh) == SB_USB) {
sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
sb_core_reset(sbh, 1 << 29);
} else
sb_core_reset(sbh, 0);
sb_setcoreidx(sbh, coreidx);
spin_unlock_irqrestore(&sbh_lock, flags);
return;
}
if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
return;
printk("PCI: Fixing up bridge\n");
/* Enable PCI bridge bus mastering */
pci_set_master(dev);
/* Enable PCI bridge BAR1 prefetch and burst */
pci_write_config_dword(dev, PCI_BAR1_CONTROL, 0x3);
}
int
pcibios_enable_device(struct pci_dev *dev, int mask)
{
ulong flags;
uint coreidx;
void *regs;
/* External PCI device enable */
if (dev->bus->number != 0)
return pcibios_enable_resources(dev);
/* These cores come out of reset enabled */
if (dev->device == SB_MIPS ||
dev->device == SB_MIPS33 ||
dev->device == SB_EXTIF ||
dev->device == SB_CC)
return 0;
spin_lock_irqsave(&sbh_lock, flags);
coreidx = sb_coreidx(sbh);
regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
if (!regs)
return PCIBIOS_DEVICE_NOT_FOUND;
/*
* The USB core requires a special bit to be set during core
* reset to enable host (OHCI) mode. Resetting the SB core in
* pcibios_enable_device() is a hack for compatibility with
* vanilla usb-ohci so that it does not have to know about
* SB. A driver that wants to use the USB core in device mode
* should know about SB and should reset the bit back to 0
* after calling pcibios_enable_device().
*/
if (sb_coreid(sbh) == SB_USB) {
sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
sb_core_reset(sbh, 1 << 29, 0);
}
/*
* USB 2.0 special considerations:
*
* 1. Since the core supports both OHCI and EHCI functions, it must
* only be reset once.
*
* 2. In addition to the standard SB reset sequence, the Host Control
* Register must be programmed to bring the USB core and various
* phy components out of reset.
*/
else if (sb_coreid(sbh) == SB_USB20H) {
if (!sb_iscoreup(sbh)) {
sb_core_reset(sbh, 0, 0);
writel(0x7FF, (ulong)regs + 0x200);
udelay(1);
}
} else
sb_core_reset(sbh, 0, 0);
sb_setcoreidx(sbh, coreidx);
spin_unlock_irqrestore(&sbh_lock, flags);
return 0;
}
