/// \brief Main function of the progam.
///
/// It's the most important function.
/// Generate the NoC system instantiating the NoC1 component.
/// Windows users: check the simulation time using 2 SYSTEMTIME variables and the function GetSystemTime from "windows.h".
/// For testing or to generate waves: use the technique shown in the code between //#INIT_WAVE and //#FINISH_WAVE. If not interested in waves, it is possible to cancel that part of code.
int sc_main (int argc,char *argv[])
{
NoC_WR *NoC1;
NoC1=new NoC_WR("NoC1");
//SYSTEMTIME now,now1;
//#INIT_WAVE
sc_trace_file* tracefile;
tracefile=sc_create_vcd_trace_file("wave");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkL,"clkL");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->clkR,"clkR");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datain,"L_datain");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datain,"R_datain");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_dataout,"L_dataout");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_dataout,"R_dataout");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_strobe_s,"L_strobe_s");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_strobe_s,"R_strobe_s");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->L_datac_s,"L_datac_s");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->R_datac_s,"R_datac_s");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_N,"save_register_N");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.save_register_P,"save_register_P");
sc_trace(tracefile,NoC1->wrapperNS[4-1][1-1]->rx_RtoL.saved_packet,"saved_packet");
sc_trace_file* tracefile2;
tracefile2=sc_create_vcd_trace_file("wave2");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkL,"clkL");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->clkR,"clkR");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datain,"L_datain");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datain,"R_datain");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_dataout,"L_dataout");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_dataout,"R_dataout");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_strobe_s,"L_strobe_s");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_strobe_s,"R_strobe_s");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->L_datac_s,"L_datac_s");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->R_datac_s,"R_datac_s");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[0],"datac_container[0]");
sc_trace(tracefile2,NoC1->wrapperWE[5-1][3-1]->rx_LtoR.datac_container[1],"datac_container[1]");
//#FINISH_WAVE
//GetSystemTime(&now);
sc_start(1000,SC_NS);
//GetSystemTime(&now1);
//cout<<(now1.wMilliseconds-now.wMilliseconds)<<endl;
//#INIT_WAVE
sc_close_vcd_trace_file(tracefile);
sc_close_vcd_trace_file(tracefile2);
//#FINISH_WAVE
return 0;
}
int sc_main(int, char **)
{
sc_signal<bool> a, b, f;
sc_clock clk("Clk", 20, SC_NS); // 时钟周期为 20ns
// 分别定义模块 NAND 和 TB 的实例，并通过局部变量（如 a、b）将这两个实例连接起来
nand NAND("NAND");
NAND.A(a);
NAND.B(b);
NAND.F(f);
tb TB("TB");
TB.clk(clk);
TB.a(a);
TB.b(b);
TB.f(f);
// 生成仿真结果波形文件
sc_trace_file *tf = sc_create_vcd_trace_file("NAND");
sc_trace(tf, NAND.A, "A");
sc_trace(tf, NAND.B, "B");
sc_trace(tf, NAND.F, "F");
sc_trace(tf, TB.clk, "CLK");
sc_start(200, SC_NS); // 仿真时长 200ns
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main (int argc, char * argv[]) {
sc_clock clk ("my_clock",1,0.5);
ControlUnitTest *control = new ControlUnitTest("ControlUnitTest");
control->clock(clk.signal());
sc_trace_file *tf = sc_create_vcd_trace_file("ControlUnitTest");
sc_trace(tf,control->clock,"clock");
sc_trace(tf,control->iRInput,"iRInput");
sc_trace(tf,control->statusBit,"statusBit");
sc_trace(tf,control->ulaOp,"ulaOP");
sc_trace(tf,control->ulaOutDemuxSel,"ulaOutDemuxSel");
sc_trace(tf,control->ulaInAMuxSel,"ulaInAMuxSel");
sc_trace(tf,control->ulaInBMuxSel,"ulaInBMuxSel");
sc_trace(tf,control->rfSel,"rfSel");
sc_trace(tf,control->rfReadWriteBit,"rfReadWriteBit");
sc_trace(tf,control->writeMemory,"writeMemory");
sc_trace(tf,control->loadRA,"loadRA");
sc_trace(tf,control->loadRB,"loadRB");
sc_trace(tf,control->loadIR,"loadIR");
sc_trace(tf,control->loadAR,"loadAR");
sc_trace(tf,control->loadPC,"loadPC");
sc_trace(tf,control->loadDR,"loadDR");
sc_start();
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> input_1, input_2, output;
sc_clock test_clock("TestClock", 10, SC_NS, 0.5);
sc_trace_file *trace_file;
stimulus stimulus_1("Stimulus");
stimulus_1.input_1(input_1);
stimulus_1.input_2(input_2);
stimulus_1.clock(test_clock);
monitor monitor_1("Monitor");
monitor_1.input_1(input_1);
monitor_1.input_2(input_2);
monitor_1.output(output);
monitor_1.clock(test_clock);
xor_ xor_1("Xor");
xor_1.input_1(input_1);
xor_1.input_2(input_2);
xor_1.output(output);
trace_file = sc_create_vcd_trace_file("wave");
sc_trace(trace_file, test_clock, "Clock");
sc_trace(trace_file, input_1, "Input_1");
sc_trace(trace_file, input_2, "Input_2");
sc_trace(trace_file, output, "Output");
sc_start();
sc_close_vcd_trace_file(trace_file);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_signal <unsigned int> sinalA, sinalB, sinalC;
sc_clock clock(" Clock", 10, SC_NS,0.5, 1, SC_NS);
Estimulos est("Estimulos");
Maior m("Maior");
est.A(sinalA);
est.B(sinalB);
est.Clk(clock);
m.A(sinalA);
m.B(sinalB);
m.C(sinalC);
sc_trace_file* Tf;
Tf = sc_create_vcd_trace_file("traces");
sc_trace (Tf,sinalA,"A");
sc_trace (Tf,sinalB,"B");
sc_trace (Tf,sinalC,"C");
sc_trace (Tf,clock,"Clk");
sc_start();
sc_close_vcd_trace_file(Tf);
return 0;
}
/**
* main
*/
int sc_main(int argc, char* argv[]) {
sc_set_time_resolution(1, SC_PS);
sc_clock clock("clk", 1, SC_NS);
// Shift reg is declared but not implemented
sc_signal<int> shiftreg_in;
sc_signal<int> shiftreg_out;
sc_trace_file *tf = sc_create_vcd_trace_file("wave");
sc_write_comment(tf, "Simulation of Shift Reg at Elaboration Time Resolution");
sc_trace(tf, clock, "Clock");
sc_trace(tf, shiftreg_in, "shiftreg_in");
sc_trace(tf, shiftreg_out, "shiftreg_out");
sc_start(30, SC_NS);
sc_close_vcd_trace_file(tf);
system("pause");
return 0;
}
int sc_main(int argc, char* argv[])
{
// Turn off warnings due to deprecated features
sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated",
sc_core::SC_DO_NOTHING);
// Declare the channel to communicate between or_gate and its TB
sc_buffer<sc_logic> A, B, C;
// MODULE INST USING POINTERS
or_gate *OR;
OR = new or_gate("OR");
OR->a(A);// NAME BINDING
OR->b(B);
OR->c(C);
TB_or_gate TB_OR("TB_OR");
TB_OR.a(A); // NAME BINDING
TB_OR.b(B);
TB_OR.c(C);
//TB_OR(A, B, C); // POSITIONAL BINDING
#ifdef WAVE
// Generate waveform
sc_trace_file *wf = sc_create_vcd_trace_file("OR_GATE");
sc_trace(wf, OR->a, "a");
sc_trace(wf, OR->b, "b");
sc_trace(wf, OR->c, "c");
#endif
sc_start(20, SC_NS);
//sc_close_vcd_trace_file(wf);
return(0);
}
int sc_main(int argc, char* argv[]) {
sc_signal<int> out_free ;
sc_signal<int> out_available ;
sc_signal<bool> out_full ;
sc_signal<bool> out_empty ;
test_fifo u_test_fifo( "u_test_fifo" ) ;
u_test_fifo.out_free ( out_free );
u_test_fifo.out_available( out_available );
u_test_fifo.out_full ( out_full );
u_test_fifo.out_empty ( out_empty );
sc_trace_file * vcd_file;
vcd_file = sc_create_vcd_trace_file( "test_fifo" );
sc_trace( vcd_file , out_free , "out_free" );
sc_trace( vcd_file , out_available , "out_available" );
sc_trace( vcd_file , out_full , "out_full" );
sc_trace( vcd_file , out_empty , "out_empty" );
sc_start(1000, SC_NS);
sc_close_vcd_trace_file( vcd_file );
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> t_a, t_b, t_cin, t_sum, t_cout;
full_adder f1 ("FullAdderWithHalfAdder");
// Positional association:
f1 << t_a << t_b << t_cin << t_sum << t_cout;
driver d1 ("GenerateWaveforms");
d1 << t_a << t_b << t_cin;
monitor mo1 ("MonitorWaveforms");
mo1 << t_a << t_b << t_cin << t_sum << t_cout;
if (! mo1.outfile) {
cerr << "ERROR: Unable to open output file," << " fa_with_ha.out!\n";
return (-2);
}
sc_trace_file *tf = sc_create_vcd_trace_file ("full_adder");
sc_trace(tf, t_a,"A");
sc_trace(tf, t_b, "B");
sc_trace(tf, t_cin, "CarryIn");
sc_trace(tf, t_sum, "Sum");
sc_trace(tf, t_cout, "CarryOut");
sc_start(100, SC_NS);
// mo1.outfile.close();
// d1.infile.close();
sc_close_vcd_trace_file (tf);
return(0);
}
int sc_main(int argc, char* argv[])
{
sc_signal<bool> din, dout;
sc_clock clk("clk",10,SC_NS,0.5,0, SC_NS,false); // Create a clock signal
delta DUT("delta"); // Instantiate Device Under Test
DUT.din(din); // Connect ports
DUT.dout(dout);
DUT.clk(clk);
sc_trace_file *fp; // Create VCD file
fp=sc_create_vcd_trace_file("wave");// open(fp), create wave.vcd file
fp->set_time_unit(100, SC_PS); // set tracing resolution to ns
sc_trace(fp,clk,"clk"); // Add signals to trace file
sc_trace(fp,DUT.q_s,"q_s");
sc_trace(fp,din,"din");
sc_trace(fp,dout,"dout");
sc_start(31, SC_NS); // Run simulation
din=true;
sc_start(31, SC_NS); // Run simulation
din=false;
sc_start(31, SC_NS); // Run simulation
sc_close_vcd_trace_file(fp); // close(fp)
return 0;
}
void anoc_init_simu() {
// Resolution time ( time stamp ) in nano second;
#ifdef NC_SYSTEMC
sc_set_time_resolution( 1, SC_NS );
#endif
// transaction generation
#ifdef TLM_TRANS_RECORD
tlm_transrecord_database::enable_global_transaction_recording();
if (tlm_transrecord_database::is_global_transaction_recording_enabled()) {
tlm_transrecord_database::open_database(DATA_BASE_NAME, SC_NS);
}
#endif // TLM_TRANS_RECORD
// open & create trace file
#ifdef TRACE_VCD
if (VCD_Record==true) {
pt_trace_file = sc_create_vcd_trace_file(VCD_FILE_NAME); // will automatically add .vcd extension
((vcd_trace_file *)pt_trace_file)->sc_set_vcd_time_unit(TIMESCALE);
}
#endif // TRACE_VCD
// Clean Stop SystemC
signal(SIGINT,anoc_close_simu); // CTRL-C
}
int sc_main(int ac, char *av[])
{
sc_trace_file *tf;
sc_signal<bool> clock;
sc_signal<int> I;
sc_signal<char> C;
sc_signal<float> F;
sc_signal<sc_logic> L;
proc1 P1("P1", clock, I, C, F, L);
tf = sc_create_vcd_trace_file("test08");
sc_trace(tf, clock, "Clock");
sc_trace(tf, I, "Int", 32);
sc_trace(tf, C, "Char", 8);
sc_trace(tf, F, "Float");
sc_trace(tf, L, "Logic");
clock.write(0);
sc_start(0, SC_NS);
for (int i = 0; i< 10; i++) {
clock.write(1);
sc_start(10, SC_NS);
clock.write(0);
sc_start(10, SC_NS);
}
sc_close_vcd_trace_file( tf );
return 0;
}
void test_miniuart()
{
sc_set_time_resolution(1, SC_NS);
sc_signal<bool> sys_clk, reset, int_rx, int_tx, txd_rxd;
sc_signal_resolved ce, rd, wr;
sc_signal_rv<2> addr;
sc_signal_rv<8> data_in;
sc_signal_rv<8> data_out;
MiniUart MiniUart_inst("MiniUart");
MiniUart_inst.sys_clk(sys_clk);
MiniUart_inst.reset(reset);
MiniUart_inst.ce(ce);
MiniUart_inst.rd(rd);
MiniUart_inst.wr(wr);
MiniUart_inst.addr(addr);
MiniUart_inst.data_in(data_in);
MiniUart_inst.data_out(data_out);
MiniUart_inst.int_rx(int_rx);
MiniUart_inst.int_tx(int_tx);
MiniUart_inst.rxd(txd_rxd);
MiniUart_inst.txd(txd_rxd);
RTL_TestBench RTL_TestBench_inst("RTL_TestBench");
RTL_TestBench_inst.sys_clk(sys_clk);
RTL_TestBench_inst.reset(reset);
RTL_TestBench_inst.ce(ce);
RTL_TestBench_inst.rd(rd);
RTL_TestBench_inst.wr(wr);
RTL_TestBench_inst.addr(addr);
RTL_TestBench_inst.data_in(data_out);
RTL_TestBench_inst.data_out(data_in);
RTL_TestBench_inst.int_rx(int_rx);
RTL_TestBench_inst.int_tx(int_tx);
sc_trace_file *tf = sc_create_vcd_trace_file("wave_miniuart");
sc_write_comment(tf, "Simulation of Mini Uart");
((vcd_trace_file*)tf)->set_time_unit(1,SC_NS); // 10exp(-9) = 1 ns
sc_trace(tf,sys_clk, "sys_clk");
sc_trace(tf,reset,"reset");
sc_trace(tf,ce,"ce");
sc_trace(tf,rd,"rd");
sc_trace(tf,wr,"wr");
sc_trace(tf,addr,"addr");
sc_trace(tf,data_in,"data_in");
sc_trace(tf,data_out,"data_out");
sc_trace(tf,int_rx,"int_rx");
sc_trace(tf,int_tx,"int_tx");
sc_trace(tf,txd_rxd,"txd_rxd");
sc_start(8, SC_MS);
sc_close_vcd_trace_file(tf);
}
testbench::testbench(sc_module_name name) {
p_inst = new processor("p_inst");
t_inst = new transactor("t_inst", 25);
tlm_bus_inst = new tlm_bus();
m_inst = new MiniUart("m_inst");
p_inst->p_slave(*tlm_bus_inst);
t_inst->p_master(*tlm_bus_inst);
t_inst->int_tx(int_tx);
t_inst->int_rx(int_rx);
t_inst->reset(reset);
t_inst->ce(ce);
t_inst->rd(rd);
t_inst->wr(wr);
t_inst->addr(addr);
t_inst->data_in(data_in);
t_inst->data_out(data_out);
m_inst->sys_clk(t_inst->sys_clk);
m_inst->int_tx(int_tx);
m_inst->int_rx(int_rx);
m_inst->reset(reset);
m_inst->ce(ce);
m_inst->rd(rd);
m_inst->wr(wr);
m_inst->addr(addr);
m_inst->data_in(data_out);
m_inst->data_out(data_in);
m_inst->txd(txd_rxd);
m_inst->rxd(txd_rxd);
tf = sc_create_vcd_trace_file("trans_trace");
sc_write_comment(tf, "Simulation of Transactor");
tf->set_time_unit(1, SC_NS);
t_inst->sys_clk.trace(tf);
sc_trace(tf, reset, "reset");
sc_trace(tf, int_rx, "int_rx");
sc_trace(tf, int_tx, "int_tx");
sc_trace(tf, txd_rxd, "txd_rxd");
sc_trace(tf, ce, "ce");
sc_trace(tf, rd, "rd");
sc_trace(tf, wr, "wr");
sc_trace(tf, addr, "addr");
sc_trace(tf, data_in, "data_in");
sc_trace(tf, data_out, "data_out");
sc_trace(tf, t_inst->p_master->getAddress(), "addr");
sc_trace(tf, t_inst->p_master->getData(), "data");
sc_trace(tf, t_inst->p_master->is_read(), "rw");
}
int sc_main(int argc, char* argv[]){
sc_signal<bool> reset;
sc_signal<bool> ld;
sc_signal<bool> lshift;
sc_signal<bool> rshift;
sc_signal<bool> leftin;
sc_signal<bool> rightin;
sc_signal<sc_bv<8> > in;
sc_signal<sc_bv<8> > out;
sc_clock clk ("clk", 2, SC_US); // a clock with a period of 2 �-sec
shiftreg sr("sr0");
sr.clk(clk);
sr.reset(reset);
sr.ld(ld);
sr.lshift(lshift);
sr.rshift(rshift);
sr.leftin(leftin);
sr.rightin(rightin);
sr.in(in);
sr.out(out);
stim st("stim0");
st.reset(reset);
st.ld(ld);
st.lshift(lshift);
st.rshift(rshift);
st.leftin(leftin);
st.rightin(rightin);
st.in(out);
st.out(in);
sc_trace_file *tf; // Signal tracing
tf=sc_create_vcd_trace_file("shiftreg"); // create new trace file
tf->set_time_unit(0.5,SC_US); // set time resolution to 0.5 �-sec (let's do a bit oversampling ;-))
sc_trace(tf,clk,"clk");
sc_trace(tf,reset,"reset");
sc_trace(tf,ld,"ld");
sc_trace(tf,lshift,"lshift");
sc_trace(tf,rshift,"rshift");
sc_trace(tf,leftin,"leftin");
sc_trace(tf,rightin,"rightin");
sc_trace(tf,in,"in");
sc_trace(tf,out,"out");
sc_start(100,SC_US); // run the simulation for 100 �-sec
sc_close_vcd_trace_file(tf); // close trace file
return 0;
};
wave::wave(sc_module_name nm) //Constructor{{{
: sc_module(nm)
{
// Process registration
SC_THREAD(wave_thread);
// temperature initialization
tracefile = sc_create_vcd_trace_file("wave");
sc_trace(tracefile,oscillate,"osc");
sc_trace(tracefile,pressure,"pressure");
sc_trace(tracefile,temperature,"temperature");
sc_trace(tracefile,cylinder,"cylinder");
}//endconstructor }}}
int sc_main(int argc, char* argv[])
{
sc_signal<bool> s_sig;
sc_signal<bool> q_sig, qn_sig;
sc_clock clk_sig("TestClock", 10, SC_NS, 0.5);
TestGenerator tg("test_generator");
tg.s_out(s_sig);
tg.clk(clk_sig);
//#define TEST_S_LATCH_V0
//#define TEST_S_LATCH_V1
#define TEST_S_LATCH_WITH_TWO_OUT
#ifdef TEST_S_LATCH_V0
SLatchV0 DUT("SLatchV0");
#endif
#ifdef TEST_S_LATCH_V1
SLatchV1 DUT("SLatchV1");
#endif
#ifdef TEST_S_LATCH_WITH_TWO_OUT
SLatchWithTwoOut DUT("SLatchWithTwoOut");
#endif
DUT.clk_in(clk_sig);
DUT.set_in(s_sig);
#ifndef TEST_S_LATCH_V0
DUT.q_out(q_sig);
DUT.qn_out(qn_sig);
#endif
sc_trace_file* p_trace_file;
p_trace_file = sc_create_vcd_trace_file("traces");
sc_trace(p_trace_file, s_sig , "set" );
sc_trace(p_trace_file, DUT.reset_sig , "reset" );
sc_trace(p_trace_file, clk_sig , "clk" );
sc_trace(p_trace_file, DUT.a_sig , "a" );
sc_trace(p_trace_file, DUT.b_sig , "b" );
sc_trace(p_trace_file, DUT.q_internal_sig , "q_internal_sig" );
sc_trace(p_trace_file, DUT.qn_internal_sig , "qn_internal_sig" );
#ifndef TEST_S_LATCH_V0
sc_trace(p_trace_file, q_sig , "q_sig" );
sc_trace(p_trace_file, qn_sig , "qn_sig" );
#endif
cout << "start simulation for " << DUT.name() << endl;
sc_start(70, SC_NS);
sc_close_vcd_trace_file(p_trace_file);
return 0;
}
//----------------------------------------------------------------------------
// Architecture implementation and test of pitch detector
//----------------------------------------------------------------------------
Arch::Arch(sc_module_name name,
int samples) :
sc_module(name),
inAdapt("inAdapt"),
outAdapt("outAdapt"),
clock("clock", 20, SC_NS), // 50 mHz
sample_clock("sample_clock", 21, SC_US), // 48 kHz
reset("reset"),
in_data("in_data"),
out_data("out_data"),
instNSDFArch("NSDFArch"),
monitor_rtl("monitor_rtl", samples, rtl_file, false),
m_samples(samples)
{
reset.write(false);
// Input adapter that wraps the fifo fir input to signals
inAdapt.clock(clock);
inAdapt.reset(reset);
inAdapt.sample_clock(sample_clock);
inAdapt.out_data(in_data);
// Timed architecture version of NSDF algorithm
instNSDFArch.clock(clock);
instNSDFArch.reset(reset);
instNSDFArch.sample_clock(sample_clock);
instNSDFArch.in_data(in_data);
instNSDFArch.out_data(out_data);
// Output adapter that wraps the fir signals to output fifo
outAdapt.clock(clock);
outAdapt.reset(reset);
outAdapt.sample_clock(sample_clock);
outAdapt.in_data(out_data);
// Monitor of filtered output result from RTL level
monitor_rtl.in(outAdapt);
// Create tacefile
tracefile = sc_create_vcd_trace_file("PitchDetector");
if (!tracefile) cout << "Could not create trace file." << endl;
else cout << "Created PitchDetector.vcd" << endl;
// Set resolution of trace file to be in 1 NS
tracefile->set_time_unit(1, SC_NS);
sc_trace(tracefile, clock.signal(), "clock");
sc_trace(tracefile, sample_clock.signal(), "sample_clock");
sc_trace(tracefile, reset, "reset");
sc_trace(tracefile, in_data, "in_data");
sc_trace(tracefile, out_data, "out_data");
}
int sc_main(int, char **)
{
sc_signal<sc_uint<ENABLESIZE> > en_n;
sc_signal<sc_uint<INPUTSIZE> > dataIn;
sc_signal<sc_uint<SELECTSIZE> > selIn;
sc_signal<sc_uint<OUTPUTSIZE> > dataOut;
sc_signal<sc_uint<OUTPUTSIZE> > flag;
sc_clock clk("Clk", 20, SC_NS);
// Connect modules ------------------------------------------
mux_8_1 MUX_8_1("MUX_8_1");
MUX_8_1.en_n(en_n);
MUX_8_1.dataIn(dataIn);
MUX_8_1.selIn(selIn);
MUX_8_1.dataOut(dataOut);
MUX_8_1.flag(flag);
tb TB("TB");
TB.clk(clk);
TB.en_n(en_n);
TB.dataIn(dataIn);
TB.selIn(selIn);
TB.dataOut(dataOut);
TB.flag(flag);
// Initialize keys ------------------------------------------
cout << "Setting up FHEW" << endl;
FHEW::Setup();
cout << "Generating secret key ... " << endl;
//LWE::SecretKey LWEsk;
LWE::KeyGen(LWEsk);
cout << "Done." << endl;
cout << "Generating evaluation key ... this may take a while ... " << endl;
//FHEW::EvalKey Ek;
FHEW::KeyGen(&Ek, LWEsk);
cout << "Done." << endl << endl;
// Create trace files ----------------------------------------
sc_trace_file *tf = sc_create_vcd_trace_file("Mux_8_1");
sc_trace(tf, MUX_8_1.en_n, "en_n");
sc_trace(tf, MUX_8_1.dataIn, "dataIn");
sc_trace(tf, MUX_8_1.selIn, "selIn");
sc_trace(tf, MUX_8_1.dataOut, "dataOut");
sc_trace(tf, MUX_8_1.flag, "flag");
sc_trace(tf, TB.clk, "CLK");
sc_start(400, SC_NS);
sc_close_vcd_trace_file(tf);
return 0;
}
int
sc_main(int argc, char *argv[])
{
// sc_clock clk1("clk1", 10, SC_NS, 0.5);
// sc_clock clk2("clk2", 12, SC_NS, 0.5);
sc_signal<bool> clk1( "clk1" );
sc_signal<bool> clk2( "clk2" );
foo FOO("FOO");
FOO.clk1(clk1);
FOO.clk2(clk2);
sc_trace_file *tf = sc_create_vcd_trace_file("test");
// sc_trace(tf, clk1.signal(), "clk1");
// sc_trace(tf, clk2.signal(), "clk2");
sc_trace(tf, clk1, "clk1");
sc_trace(tf, clk2, "clk2");
sc_start(0, SC_NS);
clk1 = 0;
clk2 = 0; // 0 ns
sc_start(3, SC_NS);
clk2 = 1; // 3 ns +
sc_start(2, SC_NS);
clk1 = 1; // 5 ns +
sc_start(4, SC_NS);
clk2 = 0; // 9 ns
sc_start(1, SC_NS);
clk1 = 0; // 10 ns
sc_start(5, SC_NS);
clk2 = 1; // 15 ns +
sc_start(0, SC_NS);
clk1 = 1; // 15 ns +
sc_start(5, SC_NS);
clk1 = 0; // 20 ns
sc_start(1, SC_NS);
clk2 = 0; // 21 ns
sc_start(4, SC_NS);
clk1 = 1; // 25 ns +
sc_start(2, SC_NS);
clk2 = 1; // 27 ns +
sc_start(3, SC_NS);
clk1 = 0; // 30 ns
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_int<4> > ain, bin, sum;
sc_signal<bool> ci,co,zflag,oflag;
sc_clock clk("clk",10,SC_NS,0.5);
adder4 DUT("addsub4");
DUT.ain(ain);
DUT.bin(bin);
DUT.ci(ci);
DUT.sum(sum);
DUT.co(co);
DUT.zf(zflag);
DUT.of(oflag);
stim STIM("stimulus");
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ci(ci);
check CHECK("checker");
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ci(ci);
CHECK.sum(sum);
CHECK.co(co);
CHECK.zflag(zflag);
CHECK.oflag(oflag);
sc_initialize();
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
sc_trace(tf, ain, "ain");
sc_trace(tf, bin, "bin");
sc_trace(tf, ci, "add/sub");
sc_trace(tf, sum, "sum");
sc_trace(tf, co, "co");
sc_trace(tf, clk, "clk");
sc_trace(tf, zflag, "zero_flag");
sc_trace(tf, oflag, "overflow_flag");
sc_start(200, SC_NS);
sc_close_vcd_trace_file(tf);
return 0; // Return OK, no errors.
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_clock clk("clock", 20.84, SC_NS);
sc_signal<bool> rst;
sc_signal<bool> data_out_wr, oe_wr;
sc_signal<sc_uint<8>> data_out, oe, data_in;
sc_signal_rv<8> pins;
gpio i_gpio("GPIO");
test_gpio i_test("TEST");
i_gpio.clk(clk);
i_gpio.rst(rst);
i_test.clk(clk);
i_test.rst(rst);
i_test.data_out(data_out);
i_test.data_out_wr(data_out_wr);
i_test.oe(oe);
i_test.oe_wr(oe_wr);
i_test.data_in(data_in);
i_test.pin(pins);
i_gpio.data_out(data_out);
i_gpio.data_out_wr(data_out_wr);
i_gpio.oe(oe);
i_gpio.oe_wr(oe_wr);
i_gpio.data_in(data_in);
i_gpio.pin(pins);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_GPIO");
sc_trace(vcd_log, clk, "Clk");
sc_trace(vcd_log, rst, "Reset_n");
sc_trace(vcd_log, pins, "Pins");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_uint<4> > ain, bin, sum;
sc_signal<bool> ci,co;
sc_signal<bool> zflag,oflag ;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
sc_trace_file *fp;
fp=sc_create_vcd_trace_file("adder_wave");
fp->set_time_unit(1, SC_PS);
sc_trace(fp,ain,"ain");
sc_trace(fp,bin,"bin");
sc_trace(fp,sum,"sum");
sc_trace(fp,ci,"ci");
sc_trace(fp,co,"co");
sc_trace(fp,zflag,"zflag");
sc_trace(fp,oflag,"oflag");
sc_trace(fp,clk,"clk");
adder DUT("adder"); // Instantiate Device Under Test
DUT.ain(ain); // Connect ports
DUT.bin(bin);
DUT.ci(ci);
DUT.sum(sum);
DUT.oflag(oflag);
DUT.zflag(zflag);
DUT.co(co);
stim STIM("stimulus"); // Instantiate stimulus generator
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ci(ci);
check CHECK("checker"); // Instantiate checker
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ci(ci);
CHECK.sum(sum);
CHECK.oflag(oflag);
CHECK.zflag(zflag);
CHECK.co(co);
sc_start(100, SC_NS); // Run simulation
return 0; // Return OK, no errors.
}
int sc_main(int argc, char* argv[])
{
sc_signal<sc_int<4> > ain, bin, sum;
sc_signal<bool> ci,co;
sc_signal<bool> oflag, zflag;
sc_clock clk("clk",10,SC_NS,0.5); // Create a clock signal
adder DUT("adder"); // Instantiate Device Under Test
DUT.ain(ain); // Connect ports
DUT.bin(bin);
DUT.ci(ci);
DUT.sum(sum);
DUT.co(co);
DUT.oflag(oflag);
DUT.zflag(zflag);
stim STIM("stimulus"); // Instantiate stimulus generator
STIM.clk(clk);
STIM.ain(ain);
STIM.bin(bin);
STIM.ci(ci);
check CHECK("checker"); // Instantiate checker
CHECK.clk(clk);
CHECK.ain(ain);
CHECK.bin(bin);
CHECK.ci(ci);
CHECK.sum(sum);
CHECK.co(co);
sc_start(SC_ZERO_TIME);
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
sc_trace(tf, ain, "A");
sc_trace(tf, bin, "B");
sc_trace(tf, sum, "SUM");
sc_trace(tf, ci, "CIN");
sc_trace(tf, co, "COUT");
sc_trace(tf, oflag, "OFlag");
sc_trace(tf, zflag, "ZFlag");
sc_trace(tf, clk, "CLOCK");
sc_start(10000, SC_NS);
sc_close_vcd_trace_file(tf);
return 0; // Return OK, no errors.
}
int sc_main(int argc, char *argv[])
{
sc_signal<bool> or_1,or_2,and_3,and_4,and_5,and_6,nor_7,CO,SUM,A,B,CI;
OR2 or1("or1");
OR2 or8("or8");
OR3 or2("or2");
AND2 and3("and3");
AND2 and4("and4");
AND2 and5("and5");
AND3 and6("and6");
NOR2 nor7("nor7");
INV inv9("inv9");
or1.a(A); or1.b(B); or1.o(or_1);
or2.a(A); or2.b(B); or2.c(CI); or2.o(or_2);
and3.a(or_1); and3.b(CI); and3.o(and_3);
and4.a(A); and4.b(B); and4.o(and_4);
and5.a(nor_7); and5.b(or_2); and5.o(and_5);
and6.a(A); and6.b(B); and6.c(CI); and6.o(and_6);
nor7.a(and_3); nor7.b(and_4); nor7.o(nor_7);
or8.a(and_5); or8.b(and_6); or8.o(SUM);
inv9.a(nor_7); inv9.o(CO);
//sc_initialize(); // initialize the simulation engine
// create the file to store simulation results
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
// 4: specify the signals we’d like to record in the trace file
sc_trace(tf, A, "A"); sc_trace(tf, B, "B");
sc_trace(tf, CI, "CI");
sc_trace(tf, SUM, "SUM"); sc_trace(tf, CO, "CO");
// 5: put values on the input signals
A=0; B=0; CI=0; // initialize the input values
sc_start(10, SC_PS);
for( int i = 0 ; i < 8 ; i++ ) // generate all input combinations
{
A = ((i & 0x1) != 0); // value of A is the bit0 of i
B = ((i & 0x2) != 0); // value of B is the bit1 of i
CI = ((i & 0x4) != 0); // value of CI is the bit2 of i
sc_start(10, SC_PS); // evaluate
}
sc_close_vcd_trace_file(tf); // close file and we’re done
return 0;
}
int sc_main(int argc, char *argv[]) {
sc_set_time_resolution(1.0, SC_NS);
sc_signal<bool> rx_dp, rx_dn, tx_dp, tx_dn;
sc_signal<bool> uart_txd, uart_rxd;
sc_signal<bool> tx_oe_nc;
ft232r i_ft232r("FT232R");
test_ft232r i_test("TEST");
i_ft232r.tx_dp(tx_dp);
i_ft232r.tx_dn(tx_dn);
i_ft232r.tx_oe(tx_oe_nc);
i_ft232r.rx_dp(rx_dp);
i_ft232r.rx_dn(rx_dn);
i_ft232r.rx_d(rx_dp);
i_ft232r.uart_txd(uart_txd);
i_ft232r.uart_rxd(uart_rxd);
i_test.txdp(rx_dp);
i_test.txdn(rx_dn);
i_test.rxdp(tx_dp);
i_test.rxdn(tx_dn);
i_test.uart_txd(uart_rxd);
i_test.uart_rxd(uart_txd);
#ifdef VCD_OUTPUT_ENABLE
sc_trace_file *vcd_log = sc_create_vcd_trace_file("TEST_FT232R");
sc_trace(vcd_log, uart_txd, "UART_TXD");
sc_trace(vcd_log, uart_rxd, "UART_RXD");
sc_trace(vcd_log, tx_dp, "USB_TXDP");
sc_trace(vcd_log, tx_dn, "USB_TXDN");
sc_trace(vcd_log, rx_dp, "USB_RXDP");
sc_trace(vcd_log, rx_dn, "USB_RXDN");
#endif
srand((unsigned int)(time(NULL) & 0xffffffff));
sc_start();
#ifdef VCD_OUTPUT_ENABLE
sc_close_vcd_trace_file(vcd_log);
#endif
return i_test.error_cnt;
}
int
sc_main (int argc, char *argv[])
{
sc_clock clk ("clk", 1, SC_US);
rng *rng1;
stimulus *st1;
rng1 = new rng ("rng");
st1 = new stimulus ("stimulus");
sc_signal < bool > reset;
sc_signal < bool > loadseed_i;
sc_signal < sc_uint < 32 > >seed_i;
sc_signal < sc_uint < 32 > >number_o;
rng1->clk (clk);
rng1->reset (reset);
rng1->loadseed_i (loadseed_i);
rng1->seed_i (seed_i);
rng1->number_o (number_o);
st1->clk (clk);
st1->reset (reset);
st1->loadseed_o (loadseed_i);
st1->seed_o (seed_i);
st1->number_i (number_o);
sc_trace_file *tf = sc_create_vcd_trace_file("rng_wave");
sc_write_comment(tf, "Random Number Generator wave trace");
tf->set_time_unit(1, SC_US);
sc_trace(tf, reset, "Reset");
sc_trace(tf, loadseed_i, "InitialSeed");
sc_trace(tf, seed_i, "Seed");
sc_trace(tf, number_o, "RandomNumber");
sc_start (1, SC_SEC);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<sc_uint<8> > A0, A1, A2, A3;
sc_signal<sc_uint<8> > outbuf;
sc_signal<sc_uint<8> > avg;
sc_clock clk("clk", 10, SC_NS, 0.5);
reduction DUT("reduction");
DUT.clk(clk);
DUT.A0(A0);
DUT.A1(A1);
DUT.A2(A2);
DUT.A3(A3);
DUT.avg(avg);
stim STIM("stimulus");
STIM.clk(clk);
STIM.A0(A0);
STIM.A1(A1);
STIM.A2(A2);
STIM.A3(A3);
outputcollect OUTCL("outputcollect");
OUTCL.clk(clk);
OUTCL.avg(avg);
check CHECK("checker");
CHECK.clk(clk);
CHECK.avg(avg);
sc_start(SC_ZERO_TIME);
sc_trace_file *tf = sc_create_vcd_trace_file("trace");
sc_trace(tf, A0, "A0");
sc_trace(tf, A1, "A1");
sc_trace(tf, A2, "A2");
sc_trace(tf, A3, "A3");
sc_trace(tf, avg, "AVG");
sc_trace(tf, clk, "CLOCK");
sc_start(10000000, SC_NS);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main(int argc, char *argv[]){
sc_signal<bool> clock, reset;
sc_signal<unsigned short int> count_val;
sc_signal<char> v_hi, v_lo;
sc_set_time_resolution(1, SC_US);
stimul stim("stimuli_mod");
stim.clk(clock);
stim.res(reset);
counter count("counter");
count.clk(clock);
count.res(reset);
count.cnt(count_val);
bcd_decoder bcd("bcd_decode");
bcd.val(count_val);
bcd.hi(v_hi);
bcd.lo(v_lo);
sc_trace_file *tf = sc_create_vcd_trace_file("traces");
sc_trace(tf, reset, "reset");
sc_trace(tf, clock, "clock");
sc_trace(tf, count_val, "counter_value");
sc_trace(tf, v_hi, "BCD_High");
sc_trace(tf, v_lo, "BCD_low");
int n_cycles;
if(argc != 2){
cout << "default n_cycles = 200\n";
n_cycles = 200;
}
else
n_cycles = atoi(argv[1]);
sc_start(n_cycles, SC_US);
sc_close_vcd_trace_file(tf);
return 0;
}
int sc_main (int argc, char * argv[]) {
sc_clock clk ("my_clock",1,0.5);
RegisterTest *rs = new RegisterTest("RegisterTest");
rs->clock(clk.signal());
sc_trace_file *tf = sc_create_vcd_trace_file("RegisterTest");
sc_trace(tf,rs->clock,"clock");
sc_trace(tf,rs->sel,"sel");
sc_trace(tf,rs->in, "in");
sc_trace(tf,rs->out, "out");
sc_trace(tf,rs->rwBit, "rwBit");
sc_start();
sc_close_vcd_trace_file(tf);
return 0;
}
