示例#1
0
U32 static_Hash_HwPerformDmaDigest(U32* pData, U32 nProcessedBytes, U32 control, U32 dmaUse)
{
   U32 bufIn_phys = virt_to_phys(pData);
   U32 dma_ch0 = OMAP3430_SMC_DMA_CH_0;   /* Hard Coded Tx Data */
   SCX_DMA_CHANNEL_PARAM ch0_parameters;
   U32 returnCode = PUBLIC_CRYPTO_OPERATION_SUCCESS;
   int sizeToProcess;

   sizeToProcess = (control & 0xFFFFFFE0)>>5;

   /* Makes sure that if the dma channels that will need to be used are currently active,
   one can reprogram it (them)  */
   scxPublicDMADisableChannel(dma_ch0);

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Reset DMA int (DMA CTRL) - The DMA int (INT CTRL) is reset by the OS */
      scxPublicDMADisableL3IRQ();
      scxPublicDMAClearL3IRQ();
   }

   /* DMA1: Mem -> HASH */
   ch0_parameters.data_type =   DMA_CSDP_Srce_Endian_little
      | DMA_CSDP_Srce_Endian_Lock_off
      | DMA_CSDP_Dest_Endian_little
      | DMA_CSDP_Dest_Endian_Lock_off
      | DMA_CSDP_Write_Mode_none_posted
      | DMA_CSDP_Dest_Burst_64B
      | DMA_CSDP_Dest_packed_off
      | DMA_CSDP_WR_Add_Trslt
      | DMA_CSDP_Src_Burst_64B
      | DMA_CSDP_Src_packed_off
      | DMA_CSDP_RD_Add_Trslt
      | DMA_CSDP_Data_32b;
   ch0_parameters.elem_count = DMA_CEN_Elts_per_Frame_SHA;
   ch0_parameters.frame_count = sizeToProcess / HASH_BLOCK_BYTES_LENGTH;

   ch0_parameters.src_amode = 1; /* post increment */
   ch0_parameters.src_start = bufIn_phys;
   ch0_parameters.src_ei = DMA_CSEI_Default;
   ch0_parameters.src_fi = DMA_CSFI_Default;

   ch0_parameters.dst_amode = 0; /* const */
   ch0_parameters.dst_start = DIGEST1_REGS_HW_ADDR + 0x30;
   ch0_parameters.dst_ei = DMA_CDEI_Default;
   ch0_parameters.dst_fi = DMA_CDFI_Default; /* source frame index */

   ch0_parameters.trigger = DMA_CCR_Mask_Channel(DMA_CCR_Channel_Mem2SHA);
   ch0_parameters.sync_mode = 0x2; /* FS =1, BS=0 => An entire frame is
                                      transferred once a DMA request is made */
   ch0_parameters.src_or_dst_synch = 0; /* Transfert is triggered by the Dest */

   dprintk(KERN_INFO "PDrvCryptoUpdateHASHWithDMA: scxPublicDMASetParams(ch0)\n");
   scxPublicDMASetParams(dma_ch0, &ch0_parameters);

	if (nProcessedBytes == 0) {
      // Reset the digest hw => Because DIGCNT should be reset : it's the only way to do so
      OUTREG32(&g_pSha1Md5Reg_t->MASK, DIGEST_MASK_SOFTRESET_BIT);

		if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pSha1Md5Reg_t->SYSSTATUS, DIGEST_SYSTATUS_RESET_DONE) != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
         return PUBLIC_CRYPTO_ERR_TIMEOUT;
      }
   }

   dprintk(KERN_INFO "PDrvCryptoUpdateHASHWithDMA: Start DMA channel %d\n", (unsigned int)dma_ch0);

   /*
    * Set the register control to start the operation
    */
   OUTREG32(&g_pSha1Md5Reg_t->CTRL, control);


   /*
    * Set the DIGCNT register
    */
   OUTREG32(&g_pSha1Md5Reg_t->DIGCNT, nProcessedBytes);


	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      scxPublicDMAEnableL3IRQ();
   }

   dprintk(KERN_INFO "PDrvCryptoUpdateHASHWithDMA: Start DMA channel %d\n", (unsigned int)dma_ch0);

   v7_dma_flush_range((int) pData, (int) pData + sizeToProcess);

   /* Start operation */
   /* Triggers operation - Interrupt, Free Running + GO (DMA on)  */
   OUTREG32(&g_pSha1Md5Reg_t->MASK,
            INREG32(&g_pSha1Md5Reg_t->MASK)|DIGEST_MASK_DMA_EN_BIT|DIGEST_MASK_IT_EN_BIT);

   scxPublicDMAStart(dma_ch0, OMAP_DMA_DROP_IRQ|OMAP_DMA_BLOCK_IRQ);

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Suspends the process until the DMA IRQ occurs */
      dprintk(KERN_INFO "PDrvCryptoUpdateHASHWithDMA: Waiting for IRQ\n");
      returnCode = scxPublicDMAWait();
	} else {
      dprintk(KERN_INFO "PDrvCryptoUpdateHASHWithDMA: Polling DMA\n");
      returnCode = scxPublicDMAPoll(dma_ch0);
   }

	if (returnCode != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
      dprintk(KERN_ERR "PDrvCryptoUpdateHASHWithDMA: Timeout\n");
      /* Do not exit function but clear properly the operation */
   }

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Acknoledge DMA interrupt */
      scxPublicDMADisableL3IRQ();
   }

   scxPublicDMAClearChannel(dma_ch0);

   /* The dma transfert is finished, now wait until the hash operation is finished. */
	if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pSha1Md5Reg_t->IRQSTAT, DIGEST_IRQSTAT_OUTPUT_READY_BIT) != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
      return PUBLIC_CRYPTO_ERR_TIMEOUT;
   }

   /* Stop clocks */
   OUTREG32(&g_pSha1Md5Reg_t->MASK,
           INREG32(&g_pSha1Md5Reg_t->MASK)&(~DIGEST_MASK_DMA_EN_BIT)&(~DIGEST_MASK_IT_EN_BIT));

    /* Clear the interrupt */
   OUTREG32(&g_pSha1Md5Reg_t->CTRL, INREG32(&g_pSha1Md5Reg_t->CTRL)&0x0000001F);/* clear length field */

   return PUBLIC_CRYPTO_OPERATION_SUCCESS;
}
示例#2
0
static U32 PDrvCryptoUpdateDESWithDMA(PUBLIC_CRYPTO_DES_DES3_CONTEXT * pDesCtx,
                        U8 * pSrc, U8 * pDest, U32 nbBlocks, U32 dmaUse)
{
   /*
    * Note: The DMA only sees physical addresses !
    */

   U32 bufIn_phys = virt_to_phys(pSrc);
   U32 bufOut_phys = virt_to_phys(pDest);

   U32 dma_ch0 = OMAP3430_SMC_DMA_CH_0;
   U32 dma_ch1 = OMAP3430_SMC_DMA_CH_1;
   SCX_DMA_CHANNEL_PARAM ch0_parameters;
   SCX_DMA_CHANNEL_PARAM ch1_parameters;
   U32 nLength = nbBlocks * DES_BLOCK_SIZE;
   U32 returnCode;

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Use=%u, Len=%u, In=0x%08x, Out=0x%08x\n",
               (unsigned int)dmaUse, (unsigned int)nLength, (unsigned int)bufIn_phys, (unsigned int)bufOut_phys);

	if (nLength == 0) {
       /* No need of setting the dma and crypto-processor */
      dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Nothing to process\n");
      return PUBLIC_CRYPTO_OPERATION_SUCCESS;
   }

	if ((bufIn_phys == 0) || (bufOut_phys == 0)) {
       dprintk(KERN_ERR "PDrvCryptoUpdateDESWithDMA: bufIn_phys/bufOut_phys NULL\n");
       return PUBLIC_CRYPTO_ERR_BAD_PARAMETERS;
   }

   /* Makes sure buffers are 4-bytes aligned */
	if (!IS_4_BYTES_ALIGNED((int)bufIn_phys) || !IS_4_BYTES_ALIGNED((int)bufOut_phys)) {
      dprintk(KERN_ERR "PDrvCryptoUpdateDESWithDMA: bufIn_phys/Out not 4 bytes aligned\n");
      return PUBLIC_CRYPTO_ERR_ALIGNMENT;
   }

   /*
    * Only one segment of the sg list to proceed --> no need of scatter gather algo
    */

   /* Makes sure that if the dma channels that will need to be used are currently active,
   one can reprogram it (them)  */
   scxPublicDMADisableChannel(dma_ch0);
   scxPublicDMADisableChannel(dma_ch1);

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Reset DMA int (DMA CTRL) - The DMA int (INT CTRL) is reset by the OS */
      scxPublicDMADisableL3IRQ();
      scxPublicDMAClearL3IRQ();
   }

   /* DMA used for Input and Output */
   OUTREG32(&g_pDESReg_t->DES_MASK,
            INREG32(&g_pDESReg_t->DES_MASK)
            | DES_MASK_DMA_REQ_OUT_EN_BIT
            | DES_MASK_DMA_REQ_IN_EN_BIT);

   /* DMA1: Mem -> DES */
   ch0_parameters.data_type =   DMA_CSDP_Srce_Endian_little
      | DMA_CSDP_Srce_Endian_Lock_off
      | DMA_CSDP_Dest_Endian_little
      | DMA_CSDP_Dest_Endian_Lock_off
      | DMA_CSDP_Write_Mode_none_posted
      | DMA_CSDP_Dest_Burst_off
      | DMA_CSDP_Dest_packed_off
      | DMA_CSDP_WR_Add_Trslt
      | DMA_CSDP_Src_Burst_off
      | DMA_CSDP_Src_packed_off
      | DMA_CSDP_RD_Add_Trslt
      | DMA_CSDP_Data_32b;
   ch0_parameters.elem_count = DMA_CEN_Elts_per_Frame_DES;

   ch0_parameters.frame_count = nbBlocks;

   ch0_parameters.src_amode = 1; /* post increment */
   ch0_parameters.src_start = bufIn_phys;
   ch0_parameters.src_ei = DMA_CSEI_Default;
   ch0_parameters.src_fi = DMA_CSFI_Default;

   ch0_parameters.dst_amode = 0; /* const */
   ch0_parameters.dst_start = DES1_REGS_HW_ADDR + 0x24;
   ch0_parameters.dst_ei = DMA_CDEI_Default;
   ch0_parameters.dst_fi = DMA_CDFI_Default; /* source frame index */

   ch0_parameters.trigger = DMA_CCR_Mask_Channel(DMA_CCR_Channel_Mem2DES);
   ch0_parameters.sync_mode = 0x2; /* FS =1, BS=0 => An entire frame is
                                      transferred once a DMA request is made */
   ch0_parameters.src_or_dst_synch = 0; /* Transfert is triggered by the Dest */

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: scxPublicDMASetParams(ch0)\n");
   scxPublicDMASetParams(dma_ch0, &ch0_parameters);

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Start DMA channel %d\n", (unsigned int)dma_ch0);

   scxPublicDMAStart(dma_ch0, OMAP_DMA_DROP_IRQ);

   /* DMA2: DES -> Mem */
   ch1_parameters.data_type =   DMA_CSDP_Srce_Endian_little
      | DMA_CSDP_Srce_Endian_Lock_off
      | DMA_CSDP_Dest_Endian_little
      | DMA_CSDP_Dest_Endian_Lock_off
      | DMA_CSDP_Write_Mode_none_posted
      | DMA_CSDP_Dest_Burst_off
      | DMA_CSDP_Dest_packed_off
      | DMA_CSDP_WR_Add_Trslt
      | DMA_CSDP_Src_Burst_off
      | DMA_CSDP_Src_packed_off
      | DMA_CSDP_RD_Add_Trslt
      | DMA_CSDP_Data_32b;
   ch1_parameters.elem_count = DMA_CEN_Elts_per_Frame_DES;
   ch1_parameters.frame_count = nbBlocks;

   ch1_parameters.src_amode = 0; /* const */
   ch1_parameters.src_start = DES1_REGS_HW_ADDR + 0x24;
   ch1_parameters.src_ei = DMA_CSEI_Default;
   ch1_parameters.src_fi = DMA_CSFI_Default;

   ch1_parameters.dst_amode = 1; /* post increment */
   ch1_parameters.dst_start =  bufOut_phys;
   ch1_parameters.dst_ei = DMA_CDEI_Default;
   ch1_parameters.dst_fi = DMA_CDFI_Default; /* source frame index */

   ch1_parameters.trigger = DMA_CCR_Mask_Channel(DMA_CCR_Channel_DES2Mem);
   ch1_parameters.sync_mode = 0x2; /* FS =1, BS=0 => An entire frame is
              transferred once a DMA request is made */
   ch1_parameters.src_or_dst_synch = 1; /* Transfert is triggered by the Src */

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: scxPublicDMASetParams(ch1)\n");
   scxPublicDMASetParams(dma_ch1, &ch1_parameters);

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      scxPublicDMAEnableL3IRQ();
   }

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Start DMA channel %d\n", (unsigned int)dma_ch1);
   scxPublicDMAStart(dma_ch1, OMAP_DMA_DROP_IRQ|OMAP_DMA_BLOCK_IRQ);

   /*
    * The input data may be in the cache only,
    * and the DMA is only working with physical addresses.
    * So flush the cache to have data coherency.
    */
   v7_dma_flush_range((u32)pSrc, (u32)(pSrc + nLength));

   /* Start operation */
   OUTREG32(&g_pDESReg_t->DES_MASK,
            INREG32(&g_pDESReg_t->DES_MASK)|DES_MASK_START_BIT);

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Suspends the process until the DMA IRQ occurs */
      dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Waiting for IRQ\n");
      returnCode = scxPublicDMAWait();
	} else {
      dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Polling DMA\n");
      returnCode = scxPublicDMAPoll(dma_ch1);
   }

	if (returnCode != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
      dprintk(KERN_ERR "PDrvCryptoUpdateDESWithDMA: Timeout\n");
      /* Do not exit function but clear properly the operation */
   }

	if (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ) {
      /* Acknoledge DMA interrupt */
      scxPublicDMADisableL3IRQ();
   }

   scxPublicDMAClearChannel(dma_ch1);

   /*
    * The dma transfert is complete
    */

   /* Stop clocks */
   OUTREG32(&g_pDESReg_t->DES_MASK,
            INREG32(&g_pDESReg_t->DES_MASK)
            &(~DES_MASK_START_BIT) );

   /* Unset DMA synchronisation requests */
   OUTREG32(&g_pDESReg_t->DES_MASK,
            INREG32(&g_pDESReg_t->DES_MASK)
            & (~DES_MASK_DMA_REQ_OUT_EN_BIT)
            & (~DES_MASK_DMA_REQ_IN_EN_BIT));

	if (returnCode != PUBLIC_CRYPTO_OPERATION_SUCCESS) {
      dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Error [0x%08x]\n", (unsigned int)returnCode);
      return returnCode;
   }

   /*
    * The output data are in the physical memory.
    * So invalidate the cache to have data coherency.
    */
   v7_dma_inv_range((u32)pDest, (u32)(pDest + nLength));

   dprintk(KERN_INFO "PDrvCryptoUpdateDESWithDMA: Success\n");

   return PUBLIC_CRYPTO_OPERATION_SUCCESS;
}