void im6402_device::device_reset()
{
m_rrc_count = 0;
m_trc_count = 0;
m_rbr = 0;
m_pe = 0;
m_fe = 0;
m_oe = 0;
set_dr(CLEAR_LINE);
set_tbre(ASSERT_LINE);
set_tre(ASSERT_LINE);
}
void im6402_device::rcv_complete()
{
receive_register_extract();
m_rbr = get_received_char();
if (LOG) logerror("IM6402 '%s' Receive Data %02x\n", tag().c_str(), m_rbr);
if (m_dr)
{
m_oe = 1;
}
set_dr(ASSERT_LINE);
}
void im6402_device::device_reset()
{
transmit_register_reset();
receive_register_reset();
m_rrc_count = 0;
m_trc_count = 0;
m_rbr = 0;
m_pe = 0;
m_fe = 0;
m_oe = 0;
set_dr(CLEAR_LINE);
set_tbre(ASSERT_LINE);
set_tre(ASSERT_LINE);
}
/*
** Hardware Breakpoints Services
*/
int dbg_hard_brk_set(offset_t addr, uint8_t type, uint8_t len, ctrl_evt_hdl_t hdlr)
{
uint8_t n;
for(n=0 ; n<DBG_HARD_BRK_NR ; n++)
if(!__hbrk_enabled(n))
{
__hbrk_setup_bp(n, type, len);
dbg_hard_brk_set_hdlr(n, hdlr);
set_dr(n, addr);
if(type == DR7_COND_X && !dbg_hard_brk_insn_enabled())
dbg_hard_brk_insn_enable();
dbg_hard_brk_enable();
debug(DBG_HARD_BRK, "set hard bp @ 0x%X\n", get_dr(n));
return VM_DONE;
}
return VM_IGNORE;
}
inline void im6402_device::receive_bit(int state)
{
if (LOG) logerror("IM6402 '%s' Receive Bit %u\n", tag(), state);
receive_register_update_bit(state);
if (is_receive_register_full())
{
receive_register_extract();
m_rbr = get_received_char();
if (LOG) logerror("IM6402 '%s' Receive Data %02x\n", tag(), m_rbr);
if (m_dr)
{
m_oe = 1;
}
set_dr(ASSERT_LINE);
}
}
inline void im6402_device::receive()
{
if (m_in_rri_func.isnull())
{
receive_register_update_bit(get_in_data_bit());
}
else
{
receive_register_update_bit(m_in_rri_func());
}
if (is_receive_register_full())
{
receive_register_extract();
m_rbr = get_received_char();
if (m_dr)
{
m_oe = 1;
}
set_dr(ASSERT_LINE);
}
}