void hsu_early_console_init(const char *s) { unsigned long paddr, port = 0; u8 lcr; /* * Select the early HSU console port if specified by user in the * kernel command line. */ if (*s && !kstrtoul(s, 10, &port)) port = clamp_val(port, 0, 2); paddr = HSU_PORT_BASE + port * 0x80; phsu = (void __iomem *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr); /* Disable FIFO */ writeb(0x0, phsu + UART_FCR); /* Set to default 115200 bps, 8n1 */ lcr = readb(phsu + UART_LCR); writeb((0x80 | lcr), phsu + UART_LCR); writeb(0x18, phsu + UART_DLL); writeb(lcr, phsu + UART_LCR); writel(0x3600, phsu + UART_MUL*4); writeb(0x8, phsu + UART_MCR); writeb(0x7, phsu + UART_FCR); writeb(0x3, phsu + UART_LCR); /* Clear IRQ status */ readb(phsu + UART_LSR); readb(phsu + UART_RX); readb(phsu + UART_IIR); readb(phsu + UART_MSR); /* Enable FIFO */ writeb(0x7, phsu + UART_FCR); }
void hsu_early_console_init(const char *s) { unsigned long paddr, port = 0; u8 lcr; int *clkctl; if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) { paddr = MERR_HSU_PORT_BASE; clkctl = (int *)set_fixmap_offset_nocache(FIX_CLOCK_CTL, MERR_HSU_CLK_CTL); } else { paddr = MFLD_HSU_PORT_BASE; clkctl = NULL; } /* * Select the early HSU console port if specified by user in the * kernel command line. */ if (*s && !kstrtoul(s, 10, &port)) port = clamp_val(port, 0, 2); paddr += port * 0x80; phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE, paddr); /* Disable FIFO */ writeb(0x0, phsu + UART_FCR); /* Set to default 115200 bps, 8n1 */ lcr = readb(phsu + UART_LCR); writeb((0x80 | lcr), phsu + UART_LCR); writeb(0x01, phsu + UART_DLL); writeb(0x00, phsu + UART_DLM); writeb(lcr, phsu + UART_LCR); writel(0x0010, phsu + UART_ABR * 4); writel(0x0010, phsu + UART_PS * 4); if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) { /* detect HSU clock is 50M or 19.2M */ if (clkctl && *clkctl & (1 << 16)) writel(0x0120, phsu + UART_MUL * 4); /* for 50M */ else writel(0x05DC, phsu + UART_MUL * 4); /* for 19.2M */ } else writel(0x0240, phsu + UART_MUL * 4); writel(0x3D09, phsu + UART_DIV * 4); writeb(0x8, phsu + UART_MCR); writeb(0x7, phsu + UART_FCR); writeb(0x3, phsu + UART_LCR); /* Clear IRQ status */ readb(phsu + UART_LSR); readb(phsu + UART_RX); readb(phsu + UART_IIR); readb(phsu + UART_MSR); /* Enable FIFO */ writeb(0x7, phsu + UART_FCR); }