/* * Flush the mmu and reset associated register to default values. */ void init_mmu(void) { #if !(XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) /* * Writing zeros to the instruction and data TLBCFG special * registers ensure that valid values exist in the register. * * For existing PGSZID<w> fields, zero selects the first element * of the page-size array. For nonexistent PGSZID<w> fields, * zero is the best value to write. Also, when changing PGSZID<w> * fields, the corresponding TLB must be flushed. */ set_itlbcfg_register(0); set_dtlbcfg_register(0); #endif init_kio(); local_flush_tlb_all(); /* Set rasid register to a known value. */ set_rasid_register(ASID_INSERT(ASID_USER_FIRST)); /* Set PTEVADDR special register to the start of the page * table, which is in kernel mappable space (ie. not * statically mapped). This register's value is undefined on * reset. */ set_ptevaddr_register(XCHAL_PAGE_TABLE_VADDR); }
/* * Flush the mmu and reset associated register to default values. */ void __init init_mmu(void) { /* Writing zeros to the <t>TLBCFG special registers ensure * that valid values exist in the register. For existing * PGSZID<w> fields, zero selects the first element of the * page-size array. For nonexistent PGSZID<w> fields, zero is * the best value to write. Also, when changing PGSZID<w> * fields, the corresponding TLB must be flushed. */ set_itlbcfg_register(0); set_dtlbcfg_register(0); flush_tlb_all(); /* Set rasid register to a known value. */ set_rasid_register(ASID_USER_FIRST); /* Set PTEVADDR special register to the start of the page * table, which is in kernel mappable space (ie. not * statically mapped). This register's value is undefined on * reset. */ set_ptevaddr_register(PGTABLE_START); }