static noinline void archosg9_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1200; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; set_muxconf_regs(); omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1380); /* Enable all clocks */ omap4_enable_all_clocks(); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ omap4_configure_mpu_dpll(&mpu); omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); omap4_configure_usb_dpll(&usb); omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); }
int board_init (void) { if (machine_is_omap_h2()) gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; else if (machine_is_omap_innovator()) gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; else gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; /* Configure MUX settings */ set_muxconf_regs (); peripheral_power_enable (); /* this speeds up your boot a quite a bit. However to make it * work, you need make sure your kernel startup flush bug is fixed. * ... rkw ... */ icache_enable (); flash__init (); ether__init (); return 0; }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with sram stack. **********************************************************/ void s_init(void) { watchdog_init(); set_muxconf_regs(); delay(100); peripheral_enable(); icache_enable(); }
void s_init(void) { /* Configure MUX settings */ set_muxconf_regs (); peripheral_power_enable (); /* this speeds up your boot a quite a bit. However to make it * work, you need make sure your kernel startup flush bug is fixed. * ... rkw ... */ icache_enable (); }
static void noinline pcm049_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; unsigned int rev = omap4_revision(); set_muxconf_regs(); #ifdef CONFIG_1024MB_DDR2RAM omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); #else omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); #endif /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ if (rev < OMAP4460_ES1_0) omap4430_scale_vcores(); else omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ if (rev < OMAP4460_ES1_0) omap4_configure_mpu_dpll(&mpu44xx); else omap4_configure_mpu_dpll(&mpu4460); omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); omap4_configure_usb_dpll(&usb); /* Enable all clocks */ omap4_enable_all_clocks(); sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); /* enable software ioreq */ sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */ sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); /* activate clock source */ sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ }
/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = is_running_in_sdram(); watchdog_init(); try_unlock_memory(); /* * Right now flushing at low MPU speed. * Need to move after clock init */ invalidate_dcache(get_device_type()); #ifdef CONFIG_L2_OFF l2_cache_disable(); #else l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); sdelay(100); prcm_init(); per_clocks_enable(); #ifdef CONFIG_USB_EHCI_OMAP ehci_clocks_enable(); #endif #ifdef CONFIG_SPL_BUILD preloader_console_init(); timer_init(); #endif if (!in_sdram) mem_init(); }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with sram stack. **********************************************************/ void s_init(void) { int in_sdram = running_in_sdram(); watchdog_init(); set_muxconf_regs(); delay(100); try_unlock_sram(); if(!in_sdram) prcm_init(); peripheral_enable(); icache_enable(); if (!in_sdram) sdrc_init(); }
int board_init (void) { /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; /* Configure MUX settings */ set_muxconf_regs (); peripheral_power_enable (); /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ toggle_backup_led(); /* Hold GSM in reset until needed */ *((volatile unsigned short *)M_CTL) &= ~1; /* * CSx timings, GPIO Mux ... setup */ /* Flash: CS0 timings setup */ *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; /* Ethernet support trough the debug board */ /* CS1 timings setup */ *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; /* this speeds up your boot a quite a bit. However to make it * work, you need make sure your kernel startup flush bug is fixed. * ... rkw ... */ icache_enable (); flash__init (); ether__init (); return 0; }
static noinline void pcaaxl2_init_lowlevel(void) { struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; unsigned int rev = omap4_revision(); set_muxconf_regs(); omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); if (rev < OMAP4460_ES1_0) omap4430_scale_vcores(); else omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); /* Configure all DPLL's at 100% OPP */ if (rev < OMAP4460_ES1_0) omap4_configure_mpu_dpll(&mpu44xx); else omap4_configure_mpu_dpll(&mpu4460); omap4_configure_iva_dpll(&iva); omap4_configure_per_dpll(&per); omap4_configure_abe_dpll(&abe); omap4_configure_usb_dpll(&usb); /* Enable all clocks */ omap4_enable_all_clocks(); sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */ sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. **********************************************************/ void s_init(void) { int i; int external_boot = 0; int in_sdram = running_in_sdram(); watchdog_init(); external_boot = (get_boot_type() == 0x1F) ? 1 : 0; /* Right now flushing at low MPU speed. Need to move after clock init */ v7_flush_dcache_all(get_device_type(), external_boot); try_unlock_memory(); if (cpu_is_3410()) { /* Lock down 6-ways in L2 cache so that effective size of L2 is 64K */ __asm__ __volatile__("mov %0, #0xFC":"=r" (i)); __asm__ __volatile__("mcr p15, 1, %0, c9, c0, 0":"=r" (i)); } #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif set_muxconf_regs(); delay(100); /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */ /* Currently SMI in Kernel on ES2 devices seems to have an isse * Once that is resolved, we can postpone this config to kernel */ setup_auxcr(get_device_type(), external_boot); prcm_init(); per_clocks_enable(); }
/********************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with sram stack. **********************************************************/ void s_init(void) { int in_sdram = running_in_sdram(); /* u32 rev = get_cpu_rev(); unused as of now.. */ watchdog_init(); try_unlock_sram(); /* Do SRAM availability first - take care of permissions too */ set_muxconf_regs(); delay(100); if (!in_sdram){ prcm_init(); } peripheral_enable(); icache_enable(); if (!in_sdram) sdrc_init(); }
/****************************************************************************** * Routine: s_init * Description: Does early system init of muxing and clocks. * - Called path is with SRAM stack. *****************************************************************************/ void s_init(void) { int in_sdram = is_running_in_sdram(); watchdog_init(); try_unlock_memory(); /* * Right now flushing at low MPU speed. * Need to move after clock init */ v7_flush_dcache_all(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif #ifdef CONFIG_L2_OFF l2cache_disable(); #else l2cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV * Currently SMI in Kernel on ES2 devices seems to have an issue * Once that is resolved, we can postpone this config to kernel */ if (get_device_type() == GP_DEVICE) setup_auxcr(); set_muxconf_regs(); delay(100); prcm_init(); per_clocks_enable(); if (!in_sdram) sdrc_init(); }