static void __maybe_unused imx28_detect_reset_source(const struct imx28_wd *p)
{
u32 reg;
reg = readl(p->regs + MXS_RTC_PERSISTENT0);
if (reg & MXS_RTC_PERSISTENT0_EXT_RST) {
writel(MXS_RTC_PERSISTENT0_EXT_RST,
p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
/*
* if the RTC has woken up the SoC, additionally the ALARM_WAKE
* bit is set. This bit should have precedence, because it
* reports the real event, why we are here.
*/
if (reg & MXS_RTC_PERSISTENT0_ALARM_WAKE) {
writel(MXS_RTC_PERSISTENT0_ALARM_WAKE,
p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
set_reset_source(RESET_WKE);
return;
}
set_reset_source(RESET_POR);
return;
}
if (reg & MXS_RTC_PERSISTENT0_THM_RST) {
writel(MXS_RTC_PERSISTENT0_THM_RST,
p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
set_reset_source(RESET_RST);
return;
}
set_reset_source(RESET_RST);
}
static int imx_detect_reset_source(void)
{
unsigned reg = read_detection_register();
if (reg & IMX_RESET_SRC_COLDSTART) {
set_reset_source(RESET_POR);
return 0;
}
if (reg & (IMX_RESET_SRC_HRDRESET | IMX_RESET_SRC_WARMSTART)) {
set_reset_source(RESET_RST);
return 0;
}
if (reg & IMX_RESET_SRC_WDOG) {
set_reset_source(RESET_WDG);
return 0;
}
/* else keep the default 'unknown' state */
return 0;
}
/**
* Initialize communication with OBC and report boot counter and reset source
* @param boot_cnt
* @return always in ERROR_OK that means no error occurs
*/
adcs_error_status init_obc_communication(uint32_t boot_cnt) {
uint8_t rst_src = 0;
pkt_pool_INIT();
HAL_reset_source(&rst_src);
set_reset_source(rst_src);
// event_boot(rst_src, boot_cnt);
/* Initialize UART2 for OBC */
HAL_UART_Receive_IT(&huart2, adcs_data.obc_uart.uart_buf, UART_BUF_SIZE);
return error_propagation(ERROR_OK);
}