void mmu_early_enable(unsigned long membase, unsigned long memsize, unsigned long ttb) { int el; /* * For the early code we only create level 1 pagetables which only * allow for a 1GiB granularity. If our membase is not aligned to that * bail out without enabling the MMU. */ if (membase & ((1ULL << level2shift(1)) - 1)) return; memset((void *)ttb, 0, GRANULE_SIZE); el = current_el(); set_ttbr_tcr_mair(el, ttb, calc_tcr(el), MEMORY_ATTRIBUTES); create_sections((void *)ttb, 0, 0, 1UL << (BITS_PER_VA - 1), UNCACHED_MEM); create_sections((void *)ttb, membase, membase, memsize, CACHED_MEM); tlb_invalidate(); isb(); set_cr(get_cr() | CR_M); }
/* * This mmu table looks as below * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 * and other Level1 Table1. * Level1 Table0 contains entries for each 1GB from 0 to 511GB. * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. */ void mmu_setup(void) { int el; u64 i, section_l1t0, section_l1t1; u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; u64 *level0_table = (u64 *)gd->arch.tlb_addr; u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); /* Invalidate all table entries */ memset(level0_table, 0, PGTABLE_SIZE); level0_table[0] = (u64)level1_table_0 | PMD_TYPE_TABLE; level0_table[1] = (u64)level1_table_1 | PMD_TYPE_TABLE; /* * set level 1 table 0, covering 0 to 512GB * set level 1 table 1, covering 512GB to 1TB */ section_l1t0 = 0; section_l1t1 = BLOCK_SIZE_L0; for (i = 0; i < 512; i++) { level1_table_0[i] = section_l1t0; if (i >= 4) level1_table_0[i] |= MEMORY_ATTR; level1_table_1[i] = section_l1t1; level1_table_1[i] |= MEMORY_ATTR; section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; } level1_table_0[0] = (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[1] = (u64)level2_table_1 | PMD_TYPE_TABLE; level1_table_0[2] = (u64)level2_table_2 | PMD_TYPE_TABLE; level1_table_0[3] = (u64)level2_table_3 | PMD_TYPE_TABLE; section_l2t0 = 0; section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ for (i = 0; i < 512; i++) { level2_table_0[i] = section_l2t0 | DEVICE_ATTR; level2_table_1[i] = section_l2t1 | DEVICE_ATTR; level2_table_2[i] = section_l2t2 | MEMORY_ATTR; level2_table_3[i] = section_l2t3 | MEMORY_ATTR; section_l2t0 += BLOCK_SIZE_L2; section_l2t1 += BLOCK_SIZE_L2; section_l2t2 += BLOCK_SIZE_L2; section_l2t3 += BLOCK_SIZE_L2; } /* flush new MMU table */ flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); /* point TTBR to the new table */ el = current_el(); set_ttbr_tcr_mair(el, gd->arch.tlb_addr, TEGRA_TCR, MEMORY_ATTRIBUTES); set_sctlr(get_sctlr() | CR_M); }
/* * This mmu table looks as below * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0 * and other Level1 Table1. * Level1 Table0 contains entries for each 1GB from 0 to 511GB. * Level1 Table1 contains entries for each 1GB from 512GB to 1TB. * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively. */ static void zynqmp_mmu_setup(void) { int el; u32 index_attr; u64 i, section_l1t0, section_l1t1; u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3; u64 *level0_table = (u64 *)gd->arch.tlb_addr; u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE); u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE)); u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE)); u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE)); u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE)); u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE)); level0_table[0] = (u64)level1_table_0 | PMD_TYPE_TABLE; level0_table[1] = (u64)level1_table_1 | PMD_TYPE_TABLE; /* * set level 1 table 0, covering 0 to 512GB * set level 1 table 1, covering 512GB to 1TB */ section_l1t0 = 0; section_l1t1 = BLOCK_SIZE_L0; index_attr = 0; for (i = 0; i < 512; i++) { level1_table_0[i] = section_l1t0; level1_table_0[i] |= attr_tbll1t0[index_attr].attr; attr_tbll1t0[index_attr].num--; if (attr_tbll1t0[index_attr].num == 0) index_attr++; level1_table_1[i] = section_l1t1; level1_table_1[i] |= DEVICE_ATTR; section_l1t0 += BLOCK_SIZE_L1; section_l1t1 += BLOCK_SIZE_L1; } level1_table_0[0] = (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[1] = (u64)level2_table_1 | PMD_TYPE_TABLE; level1_table_0[2] = (u64)level2_table_2 | PMD_TYPE_TABLE; level1_table_0[3] = (u64)level2_table_3 | PMD_TYPE_TABLE; section_l2t0 = 0; section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */ section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */ section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */ index_attr = 0; for (i = 0; i < 512; i++) { level2_table_0[i] = section_l2t0 | MEMORY_ATTR; level2_table_1[i] = section_l2t1 | MEMORY_ATTR; level2_table_2[i] = section_l2t2 | DEVICE_ATTR; level2_table_3[i] = section_l2t3 | attr_tbll2t3[index_attr].attr; attr_tbll2t3[index_attr].num--; if (attr_tbll2t3[index_attr].num == 0) index_attr++; section_l2t0 += BLOCK_SIZE_L2; section_l2t1 += BLOCK_SIZE_L2; section_l2t2 += BLOCK_SIZE_L2; section_l2t3 += BLOCK_SIZE_L2; } /* flush new MMU table */ flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); /* point TTBR to the new table */ el = current_el(); set_ttbr_tcr_mair(el, gd->arch.tlb_addr, ZYNQMP_TCR, MEMORY_ATTRIBUTES); set_sctlr(get_sctlr() | CR_M); }